AD7401YRWZ Datasheet AD7401YRWZ-REEL, AD7401YRWZ, AD7401YRWZ-REEL7 | P16-P18

Data Sheet AD7401

Rev. E | Page 15 of 20

DIGITAL FILTER

A Sinc

filter is recommended for use with the AD7401. This filter

can be implemented on an FPGA or possibly a DSP. The following

Verilog code provides an example of a Sinc

filter implementation

on a Xylinx® Spartan-II 2.5 V FPGA. This code can possibly be

compiled for another FPGA, such as an Altera® device. Note that

the data is read on the negative clock edge in this case, although

it can be read on the positive edge if preferred. Figure 29 shows the

effect of using different decimation rates with various filter types.

/*`Data is read on negative clk edge*/

module DEC256SINC24B(mdata1, mclk1, reset,

DATA);

input mclk1; /*used to clk filter*/

input reset; /*used to reset filter*/

input mdata1; /*ip data to be

filtered*/

output [15:0] DATA; /*filtered op*/

integer location;

integer info_file;

reg [23:0] ip_data1;

reg [23:0] acc1;

reg [23:0] acc2;

reg [23:0] acc3;

reg [23:0] acc3_d1;

reg [23:0] acc3_d2;

reg [23:0] diff1;

reg [23:0] diff2;

reg [23:0] diff3;

reg [23:0] diff1_d;

reg [23:0] diff2_d;

reg [15:0] DATA;

reg [7:0] word_count;

reg word_clk;

reg init;

/*Perform the Sinc ACTION*/

always @ (mdata1)

if(mdata1==0)

ip_data1 <= 0; /* change from a 0

to a -1 for 2's comp */

else

ip_data1 <= 1;

/*ACCUMULATOR (INTEGRATOR)

Perform the accumulation (IIR) at the speed

of the modulator.

ACC

05851-024

Figure 26. Accumulator

Z = one sample delay

MCLKIN = modulators conversion bit rate

always @ (posedge mclk1 or posedge reset)

if (reset)

begin

/*initialize acc registers on reset*/

acc1 <= 0;

acc2 <= 0;

acc3 <= 0;

end

else

begin

/*perform accumulation process*/

acc1 <= acc1 + ip_data1;

acc2 <= acc2 + acc1;

acc3 <= acc3 + acc2;

end

/*DECIMATION STAGE (MCLKIN/ WORD_CLK)

always @ (negedge mclk1 or posedge reset)

if (reset)

word_count <= 0;

else

word_count <= word_count + 1;

always @ (word_count)

word_clk <= word_count[7];

/*DIFFERENTIATOR (including decimation stage)

Perform the differentiation stage (FIR) at a

lower speed.

WORD_CLK

ACC3

DIFF1

DIFF3

–

DIFF2

–1

–

–1

05851-025

Figure 27. Differentiator

Z = one sample delay

WORD_CLK = output word rate

AD7401 Data Sheet

Rev. E | Page 16 of 20

always @ (posedge word_clk or posedge reset)

if(reset)

begin

acc3_d2 <= 0;

diff1_d <= 0;

diff2_d <= 0;

diff1 <= 0;

diff2 <= 0;

diff3 <= 0;

end

else

begin

diff1 <= acc3 - acc3_d2;

diff2 <= diff1 - diff1_d;

diff3 <= diff2 - diff2_d;

acc3_d2 <= acc3;

diff1_d <= diff1;

diff2_d <= diff2;

end

/* Clock the Sinc output into an output

WORD_CLK

DATADIFF3

05851-026

Figure 28. Clocking Sinc Output into an Output Register

WORD_CLK = output word rate

always @ (posedge word_clk)

begin

DATA[15] <= diff3[23];

DATA[14] <= diff3[22];

DATA[13] <= diff3[21];

DATA[12] <= diff3[20];

DATA[11] <= diff3[19];

DATA[10] <= diff3[18];

DATA[9] <= diff3[17];

DATA[8] <= diff3[16];

DATA[7] <= diff3[15];

DATA[6] <= diff3[14];

DATA[5] <= diff3[13];

DATA[4] <= diff3[12];

DATA[3] <= diff3[11];

DATA[2] <= diff3[10];

DATA[1] <= diff3[9];

DATA[0] <= diff3[8];

end

endmodule

10 100 1k1

CIMATION RATE

SNR (dB)

SINC

05851-035

Figure 29. SNR vs. Decimation Rate for Different Filter Types

Figure 29 shows a plot of SNR performance vs. decimation rate

with different filter types. Note that, for a given bandwidth

requirement, a higher MCLKIN frequency can allow higher

decimation rates to be used, resulting in higher SNR performance.

Data Sheet AD7401

Rev. E | Page 17 of 20

APPLICATIONS INFORMATION

GROUNDING AND LAYOUT

Supply decoupling with a value of 100 nF is strongly recom-

mended on both V

DD1

and V

DD2

. Decoupling on one or both

DD1

pins does not affect performance significantly. In applications

involving high common-mode transients, care must be taken to

ensure that board coupling across the isolation barrier is min-

imized. Furthermore, the board layout must be designed so any

coupling that occurs equally affects all pins on a given component

side. Failure to ensure this may cause voltage differentials between

pins to exceed the absolute maximum ratings of the device, thereby

leading to latch-up or permanent damage. Any decoupling used

must be placed as close to the supply pins as possible.

Series resistance in the analog inputs must be minimized to

avoid any distortion effects, especially at high temperatures. If

possible, equalize the source impedance on each analog input to

minimize offset. Beware of mismatch and thermocouple effects

on the analog input PCB tracks to reduce offset drift.

EVALUATING THE AD7401 PERFORMANCE

A simple standalone AD7401 evaluation board is available with

split ground planes and a board split beneath the AD7401 package

to ensure isolation. This board allows access to each pin on the

device for evaluation purposes. External supplies and all other

circuitry (such as a digital filter) must be provided by the user.

INSULATION LIFETIME

All insulation structures, subjected to sufficient time and/or

voltage, are vulnerable to breakdown. In addition to the testing

performed by the regulatory agencies, Analog Devices has carried

out an extensive set of evaluations to determine the lifetime of

the insulation structure within the AD7401.

These tests subject populations of devices to continuous cross

isolation voltages. To accelerate the occurrence of failures, the

selected test voltages are values exceeding those of normal use.

The time to failure values of these units are recorded and used

to calculate acceleration factors. These factors are then used to

calculate the time to failure under normal operating conditions.

The values shown in Table 7 are the lesser of the following

two values:

• The value that ensures at least a 50-year lifetime of

continuous use

• The maximum CSA/VDE approved working voltage

It should also be noted that the lifetime of the AD7401 varies

according to the waveform type imposed across the isolation

barrier. The iCoupler insulation structure is stressed differently

depending on whether the waveform is bipolar ac, unipolar ac,

or dc. Figure 30, Figure 31, and Figure 32 illustrate the different

isolation voltage waveforms.

RATED PEAK VOLTAGE

05851-039

Figure 30. Bipolar AC Waveform

RATED PEAK VOLTAGE

05851-040

Figure 31. Unipolar AC Waveform

RATED PEAK VOLTAGE

05851-041

Figure 32. DC Waveform

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7401YRWZ

Mfr. #:

Buy AD7401YRWZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Isolated Modulator

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7401YRWZ

AD7401YRWZ

Products related to this Datasheet