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AD7401YRWZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet AD7401
Rev. E | Page 3 of 20
SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, V
IN
+ = −200 mV to +200 mV, and V
IN
− = 0 V (single-ended); T
A
= T
MIN
to T
MAX
,
f
MCLK
= 16 MHz maximum, tested with Sinc
3
filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.
Table 1.
Parameter Y Version
1, 2
Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16 Bits min Filter output truncated to 16 bits
Integral Nonlinearity
3
±15 LSB max −40°C to +85°C; ±2 LSB typical; f
MCLK
= 20 MHz maximum
4
±25 LSB max >85°C to 105°C
±55 LSB max f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
Differential Nonlinearity
3
±0.9
LSB max
Guaranteed no missed codes to 16 bits;
f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
Offset Error
3
±0.6 mV max f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
±50 µV typ T
A
= 25°C
Offset Drift vs. Temperature
3.5 µV/°C max −40°C to +105°C
1 µV/°C typ
Offset Drift vs. V
DD1
120
µV/V typ
Gain Error
3
±1.6 mV max −40°C to +85°C
±2 mV max >85°C to 105°C
±1 mV typ f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C
Gain Error Drift vs. V
DD1
110 µV/V typ
ANALOG INPUT
Input Voltage Range
±200 mV min/mV max For specified performance; full range ±320 mV
Dynamic Input Current ±9 µA max V
IN
+ = 400 mV, V
IN
− = 0 V
DC Leakage Current ±0.5 µA max
Input Capacitance 10 pF typ
DYNAMIC SPECIFICATIONS
V
IN
+ = 5 kHz, 400 mV p-p sine
Signal-to-(Noise + Distortion) Ratio (SINAD)
3
70 dB min −40°C to +85°C; f
MCLK
= 9 MHz to 20 MHz
4
68 dB min −40°C to +85°C; f
MCLK
= 5 MHz to <9 MHz
65 dB min >85°C to 105°C
65 dB min f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
81 dB typ
Signal-to-Noise Ratio (SNR) 80 dB min −40°C to +105°C; 82 dB typ
80 dB min f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
Total Harmonic Distortion (THD)
3
−92 dB typ f
MCLK
= 20 MHz maximum
4
; V
IN
+ = −250 mV to +250 mV
Peak Harmonic or Spurious Noise (SFDR)
3
−92 dB typ
Effective Number of Bits (ENOB)
3
11.5 Bits
Isolation Transient Immunity
3
25 kV/µs min
30 kV/µs typ
LOGIC INPUTS
Input High Voltage, V
IH
0.8 × V
DD2
V min
Input Low Voltage, V
IL
0.2 × V
DD2
V max
Input Current, I
IN
±0.5 µA max
Input Capacitance, C
IN
5
10 pF max
AD7401 Data Sheet
Rev. E | Page 4 of 20
Parameter Y Version
1, 2
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD2
− 0.1 V min I
O
= −200 μA
Output Low Voltage, V
OL
0.4 V max I
O
= +200 μA
POWER REQUIREMENTS
V
DD1
4.5/5.25 V min/V max
V
DD2
3/5.5 V min/V max
I
DD1
6
12 mA max V
DD1
= 5.25 V
I
DD2
7
8 mA max V
DD2
= 5.5 V
4 mA max V
DD2
= 3.3 V
1
Temperature range is −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the Terminology section.
4
For f
MCLK
> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V
DD1
= V
DD2
= 5 V ± 5%, and T
A
= −40°C to +85°C.
5
Sample tested during initial release to ensure compliance.
6
See Figure 15.
7
See Figure 17.
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted.
1
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLKIN
2, 3
20 MHz max Master clock input frequency
5 MHz min Master clock input frequency
t
1
4
25 ns max Data access time after MCLK rising edge
t
2
4
15 ns min Data hold time after MCLK rising edge
t
3
0.4 × t
MCLKIN
ns min Master clock low time
t
4
0.4 × t
MCLKIN
ns min Master clock high time
1
Sample tested during initial release to ensure compliance
2
Mark space ratio for clock input is 40/60 to 60/40 for f
MCLKIN
to 16 MHz and 48/52 to 52/48 for f
MCLKIN
> 16 MHz to 20 MHz.
3
V
DD1
= V
DD2
= 5 V ± 5% for f
MCLKIN
> 16 MHz to 20 MHz.
4
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µA I
OL
200µA I
OH
1.6V
T
O OUTPUT
PIN
C
L
25pF
05851-002
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t
1
t
2
t
4
t
3
05851-003
Figure 3. Data Timing
Data Sheet AD7401
Rev. E | Page 5 of 20
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 3.
Parameter Symbol Value Unit Conditions
V
ISO
5000 min
V rms
1-minute duration
Minimum External Air Gap (Clearance) L(I01) 8.1 min mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.46 min mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I)
REGULATORY INFORMATION
Table 4.
UL
1
CSA VDE
2
Recognized under 1577
Component Recognition Program
1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
5000 V rms Isolation Voltage Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 630 V
rms maximum working voltage
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 891V peak
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2
In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection
limit = 5 pC).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7401YRWZ

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Analog Devices Inc.
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Analog to Digital Converters - ADC Isolated Modulator
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