AT91M63200-25AI

1
Features
Utilizes the ARM7TDMI
ARM Thumb Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE (In-circuit Emulation)
2K Bytes Internal RAM
Fully-programmable External Bus Interface (EBI)
Maximum External Address Space of 64M Bytes
Up to 8 Chip Selects
Software Programmable 8/16-bit External Data Bus
Multi-processor Interface (MPI)
High-performance External Processor Interface
512 x 16-bit Dual-port RAM
8-channel Peripheral Data Controller
8-level Priority, Individually Maskable, Vectored Interrupt Controller
5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
58 Programmable I/O Lines
6-channel 16-bit Timer/Counter
6 External Clock Inputs
2 Multi-purpose I/O Pins per Channel
3 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Support for Up to 9-bit Data Transfers
Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects
Programmable Watchdog Timer
Power Management Controller (PMC)
CPU and Peripherals Can Be Deactivated Individually
IEEE 1149.1 JTAG Boundary-scan on All Active Pins
Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V)
1.8V to 3.6V Core Operating Voltage Range
2.7V to 5.5V I/O Operating Voltage Range
-40°C to +85°C Operating Temperature Range
Available in a 176-lead TQFP Package
Description
The AT91M63200 is a member of the Atmel AT91 16/32-bit microcontroller family
which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and very low power consumption. In addition, a large number of
internally banked registers result in very fast exception handling, making the device
ideal for real-time control applications. The AT91 ARM-based MCU family also fea-
tures Atmel’s high-density, in-system programmable, nonvolatile memory technology.
The AT91M63200 has a direct connection to off-chip memory, including Flash,
through the External Bus Interface.
The Multi-processor Interface (MPI) provides a high-performance interface with an
external coprocessor or a high bandwidth peripheral.
The AT91M63200 is manufactured using the Atmel high-density CMOS technology.
By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-pro-
cessor interface and a wide range of peripheral functions on a monolithic chip, the
AT91M63200 provides a highly-flexible and cost-effective solution to many compute-
intensive multi-processor applications.
AT91
ARM
®
Thumb
®
Microcontrollers
AT91M63200
Summary
Rev. 1028DS–06/00
AT91M63200
2
Pin Configuration
Pin AT91M63200 Pin AT91M63200 Pin AT91M63200 Pin AT91M63200
1 GND 45 GND 89 GND 133 GND
2 GND 46 GND 90 GND 134 GND
3 NCS0 47 D8 91 PA19 / RXD1 135 MPI_D12
4 NCS1 48 D9 92 PA20 / SCK2 136 MPI_D13
5 NCS2 49 D10 93 PA21 / TXD2 137 MPI_D14
6 NCS3 50 D11 94 PA22 / RXD2 138 MPI_D15
7 NLB/A0 51 D12 95 PA23 / SPCK 139 PB0/MPI_NOE
8 A1 52 D13 96 PA24/MISO 140 PB1/MPI_NLB
9 A2 53 D14 97 PA25/MOSI 141 PB2/MPI_NUB
10 A3 54 D15 98 PA26/NPCS0/NSS 142 PB3
11 A4 55 PB19/TCLK0 99 PA27/NPCS1 143 PB4
12 A5 56 PB20/TIOA0 100 PA28/NPCS2 144 PB5
13 A6 57 PB21/TIOB0 101 PA29/NPCS3 145 PB6
14 A7 58 PB22/TCLK1 102 MPI_A1 146 PB7
15 VDDIO 59 VDDIO 103 VDDIO 147 VDDIO
16 GND 60 GND 104 GND 148 GND
17 A8 61 PB23/TIOA1 105 MPI_A2 149 PB8
18 A9 62 PB24/TIOB1 106 MPI_A3 150 PB9
19 A10 63 PB25/TCLK2 107 MPI_A4 151 PB10
20 A11 64 PB26/TIOA2 108 MPI_A5 152 PB11
21 A12 65 PB27/TIOB2 109 MPI_A6 153 PB12
22 A13 66 PA0/TCLK3 110 MPI_A7 154 PB13
23 A14 67 PA1/TIOA3 111 MPI_A8 155 PB14
24 A15 68 PA2/TIOB3 112 MPI_A9 156 PB15
25 A16 69 PA3/TCLK4 113 MPI_NCS 157 PB16
26 A17 70 PA4/TIOA4 114 MPI_RNW 158 PB17/MCKO
27 A18 71 PA5/TIOB4 115 MPI_BR 159 NWDOVF
28 A19 72 PA6/TCLK5 116 MPI_BG 160 MCKI
29 VDDIO 73 VDDIO 117 VDDIO 161 VDDIO
30 GND 74 GND 118 GND 162 GND
31 A20/CS7 75 PA7/TIOA5 119 MPI_D0 163 PB18/BMS
32 A21/CS6 76 PA8/TIOB5 120 MPI_D1 164 JTAGSEL
33 A22/CS5 77 PA9/IRQ0 121 MPI_D2 165 TMS
34 A23/CS4 78 PA10/IRQ1 122 MPI_D3 166 TDI
35 D0 79 PA11/IRQ2 123 MPI_D4 167 TDO
36 D1 80 PA12/IRQ3 124 MPI_D5 168 TCK
37 D2 81 PA13/FIQ 125 MPI_D6 169 NTRST
38 D3 82 PA14/SCK0 126 MPI_D7 170 NRST
39 D4 83 PA15/TXD0 127 MPI_D8 171 NWAIT
40 D5 84 PA16/RXD0 128 MPI_D9 172 NOE/NRD
41 D6 85 PA17/SCK1 129 MPI_D10 173 NWE/NWR0
42 D7 86 PA18/TXD1/NTRI 130 MPI_D11 174 NUB/NWR1
43 VDDCORE 87 VDDCORE 131 VDDCORE 175 VDDCORE
44 VDDIO 88 VDDIO 132 VDDIO 176 VDDIO
AT91M63200
3
Pin Description
Module Name Function Type
Active
Level Comments
EBI
A0 - A23 Address Bus Output All valid after reset
D0 - D15 Data Bus I/O
CS4 - CS7 Chip Select Output High A23 - A20 after reset
NCS0 - NCS3 Chip Select Output Low
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Lower Byte 1 Write Signal Output Low Used in Byte Write option
NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NLB Lower Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input Sampled during reset
MPI
MPI_NCS Chip Select Input Low
MPI_RNW Read Not Write Signal Input
MPI_BR
Bus Request From External
Processor
Input High
MPI_BG Bus Grant To External Processor Output High
MPI_NOE Output Enable Input Low
MPI_NLB Lower Byte Select Input Low
MPI_NUB Upper Byte Select Input Low
MPI_A1 - MPI_A9 Address Bus Input
MPI_D0 - MPI_D15 Data Bus I/O
AIC
IRQ0 - IRQ3 External Interrupt Request Input PIO-controlled after reset
FIQ Fast External Interrupt Request Input PIO-controlled after reset
Timer
TCLK0 - TCLK5 Timer External Clock Input PIO-controlled after reset
TIOA0 - TIOA5 Multipurpose Timer I/O Pin A I/O PIO-controlled after reset
TIOB0 - TIOB5 Multipurpose Timer I/O Pin B I/O PIO-controlled after reset
USART
SCK0 - SCK2 External Serial Clock I/O PIO-controlled after reset
TXD0 - TXD2 Transmit Data Output Output PIO-controlled after reset
RXD0 - RXD2 Receive Data Input Input PIO-controlled after reset
SPI
SPCK SPI Clock I/O PIO-controlled after reset
MISO Master In Slave Out I/O PIO-controlled after reset
MOSI Master Out Slave In I/O PIO-controlled after reset
NSS Slave Select Input Low PIO-controlled after reset
NPCS0 - NPCS3 Peripheral Chip Select Output Low PIO-controlled after reset
PIO
PA0 - PA29 Programmable I/O Port A I/O Input after reset
PB0 - PB27 Programmable I/O Port B I/O Input after reset
WD NWDOVF Watchdog Timer Overflow Output Low Open-drain
Clock
MCKI Master Clock Input Input Schmitt trigger
MCKO Master Clock Output Output
Reset NRST Hardware Reset Input Input Low Schmitt trigger, internal pull-up

AT91M63200-25AI

Mfr. #:
Manufacturer:
Description:
IC MCU 16/32BIT ROMLESS 176TQFP
Lifecycle:
New from this manufacturer.
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