AT91M63200
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EBI: External Bus Interface
The EBI generates the signals that control the access to
the external memory or peripheral devices. The EBI is fully
programmable and can address up to 64M bytes. It has
eight chip selects and a 24-bit address bus, the upper four
bits of which are multiplexed with a chip select.
The 16-bit data bus can be configured to interface with 8-
or 16-bit external devices. Separate read and write control
signals allow for direct memory and peripheral interfacing.
The EBI supports different access protocols, allowing sin-
gle clock cycle memory accesses.
The main features are:
• External memory mapping
• Up to 8 chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
MPI: Multi-processor Interface
The AT91M63200 features a second bus interface that is
dedicated to parallel data exchange with an external pro-
cessing device. The MPI features a 1-Kbyte dual-port RAM
memory and memory access arbitration logic. The ARM
processor core and the external processor can both read
and write to the dual-port RAM memory.
AIC: Advanced Interrupt Controller
The AT91M63200 has an 8-level priority, individually
maskable, vectored interrupt controller. This feature sub-
stantially reduces the software and real-time overhead in
handling internal and external interrupts.
The interrupt controller is connected to the NFIQ (fast inter-
rupt request) and the NIRQ (standard interrupt request)
inputs of the ARM7TDMI processor. The processor’s NFIQ
line can only be asserted by the external fast interrupt
request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the
external interrupt request lines: IRQ0 to IRQ3.
An 8-level priority encoder allows the customer to define
the priority between the different NIRQ interrupt sources.
Internal sources are programmed to be level sensitive or
edge triggered. External sources can be programmed to be
positive or negative edge triggered or high- or low-level
sensitive.
PIO: Parallel I/O Controller
The AT91M63200 features 58 programmable I/O lines. 14
pins on the AT91M63200 are dedicated as general-pur-
pose I/O pins. Other I/O lines are multiplexed with on-chip
peripheral I/O signals in order to optimize the use of avail-
able package pins. The I/O lines are controlled by two sep-
arate and identical PIO controllers (PIOA and PIOB). Each
PIO controller also provides an internal interrupt signal to
the Advanced Interrupt Controller (AIC).
USART: Universal
Synchronous/Asynchronous
Receiver/Transmitter
The AT91M63200 provides three identical, full-duplex, uni-
versal synchronous/asynchronous receiver/transmitters
that interface to the APB and are connected to the Periph-
eral Data Controller.
The main features are:
• Programmable baud rate generator
• Parity, framing and overrun error detection
• Line break generation and detection
• Automatic echo, local loopback and remote loopback
channel modes
• Multi-drop mode: address detection and generation
• Interrupt generation
• Two dedicated peripheral data controller channels
• 5-, 6-, 7-, 8- and 9-bit character length
SPI: Serial Peripheral Interface
The AT91M63200 features an SPI, which provides commu-
nication with external devices in master or slave mode.
The SPI has four external chip selects that can be con-
nected to up to 15 devices. The data length is programma-
ble, from 8- to 16-bit.
As for the USART, a 2-channel PDC is used to move data
directly between memory and the SPI without CPU inter-
vention for maximum real-time processing throughput.
