8P34S1208NBGI Datasheet 8P34S1208NBGI, 8P34S1208NBGI8 | P1-P3

DATA SHEET

1:8 LVDS Output 1.8V Fanout Buffer IDT8P34S1208I

General Description

The IDT8P34S1208I is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The

IDT8P34S1208I is characterized to operate from a 1.8V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the IDT8P34S1208I ideal for those clock

distribution applications demanding well-defined performance and

repeatability. Two selectable differential inputs and eight low skew

outputs are available. The integrated bias voltage reference enables

easy interfacing of single-ended signals to the device inputs. The

device is optimized for low power consumption and low additive

phase noise.

Features

• Eight low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential CLK, nCLK pairs can accept the following differential

input levels: LVDS, CML

• Maximum input clock frequency: 1.2GHz (maximum)

• LVCMOS/LVTTL interface levels for the control input select pin

• Output skew: 20ps (typical)

• Propagation delay: 315ps (typical)

• Low additive phase jitter, RMS; f

REF

= 156.25MHz, V

= 1V,

12kHz - 20MHz: 41fs (typical)

• Full 1.8V supply voltage

• Lead-free (RoHS 6), 28-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature

Block Diagram. Pin Assignment

REF

REF0

CLK0

nCLK0

CLK1

nCLK1

SEL

REF1

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

Voltage

Reference

Voltage

Reference

nQ3

nQ2

nQ1

21 20 19 18 17 16 15

IDT8P34S1208I

28-lead VFQFN

5.0mm x 5.0mm x 0.75mm

package body

3.25mm x 3.25mm ePad Size

NB Package

Top View

22 14

GND

nQ4

23 13

nQ0

24 12

nQ5

25 11

REF0

26 10

nCLK0

nQ6

27 9

CLK0

28 8

1234567

GND

nQ7

SEL

CLK1

nCLK1

REF1

IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Note 1.

1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number Name Type Description

1, 14 GND Power

Power supply pin.

2, 3 Q7, nQ7 Output

Differential output pair 7. LVDS interface levels.

4 SEL Input Pulldown

Reference select control pin. See Table 3 for function. LVCMOS/LVTTL

interface levels.

5 CLK1 Input Pulldown

Non-inverting differential clock/data input 1.

6 nCLK1 Input

Pullup/

Pulldown

Inverting differential clock/data input 1. V

/2 default when left floating.

REF1

Output

Bias voltage reference. Provides an input bias voltage for the CLK1, nCLK1

input pair in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

8, 15, 28 V

Power

Power supply pin.

9 CLK0 Input Pulldown

Non-inverting differential clock/data input 0.

10 nCLK0 Input

Pullup/

Pulldown

Inverting differential clock/data input 0. V

/2 default when left floating.

11 V

REF0

Output

Bias voltage reference. Provides an input bias voltage for the CLK0, nCLK0

input pair in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

12, 13 Q0, nQ0 Output

Differential output pair 0. LVDS interface levels.

16, 17 Q1, nQ1 Output

Differential output pair 1. LVDS interface levels.

18, 19 Q2, nQ2 Output

Differential output pair 2. LVDS interface levels.

20, 21 Q3, nQ3 Output

Differential output pair 3. LVDS interface levels.

22, 23 Q4, nQ4 Output

Differential output pair 4. LVDS interface levels.

24, 25 Q5, nQ5 Output

Differential output pair 5. LVDS interface levels.

26, 27 Q6, nQ6 Output

Differential output pair 6. LVDS interface levels.

Table 2. Pin Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input Capacitance 2 pF

PULLDOWN

Input Pulldown Resistor 51 k

PULLUP

Input Pullup Resistor 51 k

Table 3. SEL Input Function Table

Note 1.

1. SEL is an asynchronous control.

Input

OperationSEL

0 CLK0, nCLK0 is the selected differential clock input.

1 CLK1, nCLK1 is the selected differential clock input.

IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

NOTE 1: According to JEDEC JS-001-2012/JESD22-C101E.

DC Electrical Characteristics

Item Rating

Supply Voltage, V

4.6V

Inputs, V

-0.5V to V

+ 0.5V

Outputs, I

Continuous Current

Surge Current

10mA

15mA

Input Sink/Source, I

REF

±2mA

Maximum Junction Temperature, T

J,MAX

125°C

Storage Temperature, T

STG

-65°C to 150°C

ESD - Human Body Model, NOTE 1 2000V

ESD - Charged Device Model, NOTE 1 1500V

Table 4A. Power Supply DC Characteristics, V

= 1.8V ± 5%, T

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Power Supply Voltage 1.71 1.8 1.89 V

Power Supply Current Q0 to Q7 terminated 100 between nQx, Qx 120 140 mA

Table 4B. LVCMOS/LVTTL DC Characteristics, V

= 1.8V ± 5%, T

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input High Voltage V

* 0.65 V

+ 0.3 V

Input Low Voltage -0.3 V

* 0.35 V

Input High Current SEL V

= V

= 1.89V 150 µA

Input Low Current SEL V

= 1.89V, V

= 0V -10 µA

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8P34S1208NBGI

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Manufacturer:

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Description:

Clock Drivers & Distribution 1:8 LVDS Output 1.8V Fanout Buffer

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