IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 7 ©2014 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
Additive Phase Jitter @ 156.25MHz
10kHz to 20MHz – 41fs (typical)
Offset from Carrier Frequency (Hz)
SSB Phase Noise dBc/Hz
IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 8 ©2014 Integrated Device Technology, Inc.
Parameter Measurement Information
1.8V LVDS Output Load Test Circuit
Input Skew
Part-to-Part Skew
Differential Input Level
Output Skew
Pulse Skew
V
DD
t
PD2
t
PD1
tsk(i) = |t
PD1
- t
PD2
|
tsk(i)
nCLK1
CLK1
nQ[0:7]
Q[0:7]
nCLK0
CLK0
tsk(pp)
Part 1
Part 2
Qx
nQx
Qy
nQy
V
DD
GND
nCLK[0:1]
CLK[0:1]
Qx
nQx
Qy
nQy
t
PLH
t
PHL
tsk(p)
=
|t
PHL
-
t
PLH
|
CLK[0:1]
nCLK[0:1]
Qy
nQy
IDT8P34S1208I Data Sheet 1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014 9 ©2014 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
Propagation Delay
Output Rise/Fall Time
Differential Output Voltage Setup
MUX Isolation
Output Rise/Fall Time
Offset Voltage Setup
t
PD
nQ[0:7]
Q[0:7]
nCLK[0:1]
CLK[0:1]
nQ[0:7]
Q[0:7]
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX
_ISOLATION
= A0 – A1
(fundamental)
Frequency
ƒ
MUX selects other input
MUX selects active
input clock signal
A1
nQ[0:7]
Q[0:7]

8P34S1208NBGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1:8 LVDS Output 1.8V Fanout Buffer
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New from this manufacturer.
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