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UJA1075ATW/5V0WD,1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 25 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
The transceiver is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates
from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
6.8.1 LIN operating modes
6.8.1.1 Active mode
The LIN transceiver will be in Active mode when:
• the SBC is in Normal mode (MC = 10 or 11) and
• the transceiver is enabled (STBCL = 0; see Table 6) and
• the battery voltage (V
BAT
) is above the LIN undervoltage recovery threshold, V
uvr(LIN)
.
In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin.
The receiver detects data streams on the LIN bus pin (LIN) and transfers them to the
microcontroller via pin RXDL (see Figure 1
) - LIN recessive is represented by a HIGH
level on RXDL, LIN dominant by a LOW level.
The transmit data streams of the protocol controller at the TXDL input (pin TXDL) are
converted by the transmitter into bus signals with optimized slew rate and wave shaping to
minimize EME.
6.8.1.2 Lowpower/Off modes
The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCL = 1 (see Table 6
). The LIN transceiver can be woken up remotely via pin LIN in
Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceiver
will be in Off mode if bit STBCL = 0. The LIN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
Filters at the receiver inputs prevent unwanted wake-up events due to automotive
transients or EMI.
The wake-up event must remain valid for at least the minimum dominant bus time for
wake-up of the LIN transceiver, t
wake(busdom)min
(see Table 11).
Fig 11. Typical master application Fig 12. Typical slave application
UJA1075A
GND
015aaa23
LIN
LIN wire
DLIN
BAT
to supply
R
master
1 kΩ
C
master
UJA1075A
GND
015aaa23
3
LIN
LIN wire
DLIN
BAT
to supply
R
slave
30 kΩ
C
slave
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 26 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
6.8.2 Fail-safe features
6.8.2.1 General fail-safe features
The following fail-safe features have been implemented:
• Pin TXDL has an internal pull-up towards V
V1
to guarantee a safe, defined state if this
pin is left floating
• The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
• A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
6.8.2.2 TXDL dominant time-out function
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if TXDL is forced permanently LOW
by a hardware and/or software application failure. The timer is triggered by a negative
edge on pin TXDL. If the pin remains LOW for longer than the TXDL dominant time-out
time (t
to(dom)TXDL
), the transmitter is disabled, driving the bus lines to a recessive state.
The timer is reset by a positive edge on the TXDL pin.
6.9 Local wake-up input
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register Table 6
). These bits can also be used to disable
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4
).
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
Fig 13. Wake-up pin sampling synchronized with WBIAS signal
Wake-up int
WAKEx pin
WBIAS pin
WBIASI
(internal)
enable bias disable bias
disable bias
wake level latched
015aaa07
8
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 27 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting
bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are
sampled continuously). The sampling will be performed on the rising edge of WBIAS (see
Figure 13
). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit
(WBC) in the Mode_Control register.
Figure 14
shows a typical circuit for implementing cyclic sampling of the wake-up inputs.
6.10 Interrupt output
Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least
one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit
in the Int_Status register (Table 7
). Clearing bits LWI and CWI in Standby mode only
clears the interrupt status bits and not the pending wake-up. The pending wake-up is
cleared on entering Normal mode and when the corresponding standby control bit
(STBCC or STBCL) is 0.
On devices that contain a watchdog, the CI is enabled when the watchdog switches to
Timeout mode while the SBC is in Standby mode or Normal mode (provided pin
WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode.
The CI is provided to alert the microcontroller when the watchdog overflows in Timeout
mode. The CI will wake up the microcontroller from a μC standby mode. After polling the
Int_Status register, the microcontroller will be aware that the application is in cyclic wake
up mode. It can then perform some checks on CAN and LIN before returning to the μC
standby mode.
6.11 Temperature protection
The temperature of the SBC chip is monitored in Normal and Standby modes. If the
temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven
LOW and limp home is activated. In addition, the voltage regulators and the CAN and LIN
Fig 14. Typical application for cyclic sampling of wake-up signals
UJA1075A
WAKE1
WAKE2
BAT
WBIAS
015aaa18
3
47 kΩ
47 kΩ
PDTA144E
t
sample of
WAKEx
sample of
WAKEx
sample of
WAKEx
GND
biasing of
switches
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

UJA1075ATW/5V0WD,1

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Buy UJA1075ATW/5V0WD,1
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC Hi Spd CAN Transcvr 4.5V-28V 6us
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New from this manufacturer.
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