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UJA1075ATW/5V0WD,1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 31 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
8. Thermal characteristics
Layout conditions for R
th(j-a)
measurements: board finish thickness 1.6 mm ±10 %, double-layer
board, board dimensions 129 mm × 60 mm, board material FR4, Cu thickness 0.070 mm, thermal
via separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias 0.025 mm.
Optional heat sink top layer of 3.5 mm × 25 mm will reduce thermal resistance (see Figure 16
).
Fig 15. HTSSOP PCB
PCB copper area:
(bottom layer)
2 cm
2
PCB copper area:
(bottom layer)
8 cm
2
015aaa137
optional heatsink top layer
optional heatsink top layer
optional heatsink top layer
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 32 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.
[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with
two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the
first inner copper layer.
Fig 16. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper
area
Table 9. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to
ambient
single-layer board
[1]
78 K/W
four-layer board
[2]
36 K/W
PCB Cu heatsink area (cm
2
)
0 108462
015aaa138
50
70
90
R
th(j-a)
(K/W)
30
without heatsink top layer
with heatsink top layer
UJA1075A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 02 — 28 January 2011 33 of 54
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
9. Static characteristics
Table 10. Static characteristics
T
vj
=
−
40
°
C to +150
°
C; V
BAT
=4.5V to 28V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN
= 500
Ω
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all voltages
are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply; pin BAT
V
BAT
battery supply voltage 4.5 - 28 V
I
BAT
battery supply current MC = 00 (Standby; V1 on, V2 off)
STBCC = STBCL = 1 (CAN/LIN
wake-up enabled)
WIC1 = WIC2 = 11 (WAKE interrupts
enabled); 7.5 V < V
BAT
<28V
I
V1
=0mA; V
RSTN
= V
SCSN
=V
V1
V
TXDL
=V
TXDC
=V
V1
; V
SDI
=V
SCK
=0V
T
vj
= −40 °C-8398μA
T
vj
=25°C-7688μA
T
vj
= 150 °C-6880μA
MC = 01 (Sleep; V1 off, V2 off)
STBCC = STBCL = 1 (CAN/LIN
wake-up enabled)
WIC1 = WIC2 = 11 (WAKE interrupts
enabled)
7.5 V < V
BAT
<28V; V
V1
=0V
T
vj
= −40 °C-6071μA
T
vj
=25°C-5665μA
T
vj
= 150 °C-5159μA
contributed by LIN wake-up receiver
STBCL = 1
V
LIN
=V
BAT
5.5 V < V
BAT
<28V
-1.12 μA
contributed by CAN wake-up receiver
STBCC = 1; V
CANH
=V
CANL
=2.5V
5.5 V < V
BAT
<28V
1613μA
contributed by WAKEx pin edge
detectors
WIC1 = WIC2 = 11
V
WAKE1
=V
WAKE2
=V
BAT
0510μA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

UJA1075ATW/5V0WD,1

Mfr. #:
Buy UJA1075ATW/5V0WD,1
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC Hi Spd CAN Transcvr 4.5V-28V 6us
Lifecycle:
New from this manufacturer.
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