MLX90288
SMD Programmable Linear Hall Sensor IC
Featuring Analog Ratiometric Output
3901090288 Page 7 of 19
Rev 002 May/12
5.6 Diagnostic Specification
Operating rating valid for T
A
= – 40°C to + 85°C & V
DD
= + 4.5V to + 5.5V (unless specified otherwise).
ADC Clipping Signaling
(1)
DIAG
CLIP
DIAGINFAULT = 0 - - V
%V
DIAGINFAULT = 1 V
- - %V
ADC Clipping Criterion
(1)
N
CLIP
ADC clipping count
before Diagnostic is set
- 4 - Count
CRC Fail Signaling DIAG
PAR
DIAGINFAULT = 0 - - V
%V
DIAGINFAULT = 1 V
- - %V
CRC Fail Criterion N
CRC
CRC Fail count before
Diagnostic is set
- 3 - Count
Broken V
V
Over R
range - - V
%V
Broken V
V
Over R
range - - V
%V
Table 6: Diagnostic Specification
(1) ADC clipping is only flagged if the FAULTONCLIP bit in EEPROM is set. If the bit is cleared, the ADC
will clamp at either the maximum code or the minimum code, depending on the clipping condition.
Reporting after 4 sequential clipping conditions is required for an EMC robust design. Clipping
reporting does not apply to ADC values of the temperature signal.
(2) Diagnostics that are the result of a passive settling because the output stage becomes high impedant
(such as broken wire) are governed by the RC time constant of the capacitive load on the output and
the R
PD
resistor at ECU side. The OBD detection time is negligible in comparison to the settling time
in case of a broken wire. The settling time should be taken as 4 times the RC time constant. E.g. with
a load of 330nF and 330kOhm, the RC time constant equals 109ms. Settling time then corresponds
to 4 RC time constants, i.e. 436ms.
5.7 Startup, Undervoltage, Overvoltage and Reset Specification
During power-up (supply rising from 0V upwards) the MLX90288 remains in a zone where the output is
undefined (grey triangular area in the plot) because there is no active circuitry putting the output stage in a
specific condition. Most likely the output remains close to the low rail because of the passive external pull-
down, but it can not be predicted what happens exactly inside the IC at this point. This is also depicted in the
signal waveforms of Figure 2.
The POR phase is the phase where the supply is still below V
PORRISE
, but above the undefined region. In this
case the digital is in a reset state, which puts all flip-flops in a known state, and the output is high impedant.
Due to the external pull-down resistive load, the output is at the low rail.
When the supply rises above the V
PORRISE
threshold (which has built-in hysteresis: for the falling edge,
V
PORFALL
), an initialization occurs which includes loading all EEPROM settings into RAM. After this
initialization phase, the chip will start its FSM program and provide a valid output signal, for as long as the
supply voltage is above the V
UNDERRISE
threshold (which has built-in hysteresis: for the falling edge,
V
UNDERFALL
). If the supply is below this threshold, the output remains in high impedant state, corresponding to
an output voltage at the low rail.
Whenever the MLX90288 goes from normal operation to undervoltage or via undervoltage to reset state, and
vice versa, the output has a settling time which is a function of both the output load and the driving capability.
On top of this, there is a startup time (t
STARTUP
) in case the chip comes out of reset.
