MAX1470EUI+ Datasheet MAX1470EUI+, MAX1470EUI+T | P7-P9

where:

PARASITICS

and C

PARASITICS

include inductance and

capacitance of the PC board traces, package pins,

mixer input impedance, LNA output impedance, etc.

These parasitics at high frequencies cannot be ignored

and can have a dramatic effect on the tank filter center

frequency. Lab experimentation should be done to opti-

mize the center frequency of the tank.

Mixer

A unique feature of the MAX1470 is the integrated

image rejection of the mixer. This device was designed

to eliminate the need for a costly front-end SAW filter for

many applications. The advantage of not using a SAW

filter is increased sensitivity, simplified antenna match-

ing, less board space, and lower cost.

The mixer cell is a pair of double-balanced mixers that

perform an IQ downconversion of the 315MHz RF input

to the 10.7MHz IF with low-side injection (i.e., f

= f

- f

). The image rejection circuit then combines these

signals to achieve ~50dB of image rejection over the

full temperature range. Low-side injection is required

due to the on-chip image-rejection architecture. The IF

output is driven by a source-follower, biased to create a

driving impedance of 330Ω to interface with an off-chip

330Ω ceramic IF filter. The voltage conversion gain dri-

ving a 330Ω load is approximately 13dB.

Phase-Lock Loop

The PLL block contains a phase detector, charge

pump/integrated loop filter, VCO, asynchronous 64x

clock divider, and crystal oscillator. This PLL does not

require any external components. The quadrature VCO

is centered at the nominal LO frequency of 304.3MHz.

For an input RF frequency of 315MHz, a reference fre-

quency of 4.7547MHz is needed for a 10.7MHz IF fre-

quency (low-side injection is required). The relationship

between the RF, IF, and reference frequencies is given

by:

REF

= (f

- f

) / 64

To allow the smallest possible IF bandwidth (for best

sensitivity), the tolerance of the reference must be mini-

mized.

Intermediate Frequency

The IF section presents a differential 330Ω load to pro-

vide matching for the off-chip ceramic filter. The inter-

nal five AC-coupled limiting amplifiers produce an

overall gain of approximately 65dB, with a bandpass-fil-

ter-type response centered near the 10.7MHz IF fre-

quency with a 3dB bandwidth of approximately

11.5MHz. The RSSI circuit demodulates the IF to base-

band by producing a DC output proportional to the log

of the IF signal level with a slope of approximately

15mV/dB (see Typical Operating Characteristics).

Applications Information

Crystal Oscillator

The XTAL oscillator in the MAX1470 is designed to pre-

sent a capacitance of approximately 3pF between

XTAL1 and XTAL2. If a crystal designed to oscillate

with a different load capacitance is used, the crystal is

pulled away from its stated operating frequency, intro-

ducing an error in the reference frequency. Crystals

designed to operate with higher differential load capac-

itance always pull the reference frequency higher. For

example, a 4.7547MHz crystal designed to operate

with a 10pF load capacitance oscillates at 4.7563MHz

with the MAX1470, causing the receiver to be tuned to

315.1MHz rather than 315.0MHz, an error of about

100kHz, or 320ppm.

In actuality, the oscillator pulls every crystal. The crys-

tal’s natural frequency is really below its specified fre-

quency, but when loaded with the specified load

capacitance, the crystal is pulled and oscillates at its

specified frequency. This pulling is already accounted

for in the specification of the load capacitance.

Additional pulling can be calculated if the electrical

parameters of the crystal are known. The frequency

pulling is given by:

where:

is the amount the crystal frequency is pulled in ppm.

is the motional capacitance of the crystal.

case

is the case capacitance.

spec

is the specified load capacitance.

load

is the actual load capacitance.

ƒ=

−













case load case spec

CC CC2

LLL

CCC

TOTAL PARASITICS

ƒ=

2π LC

TOTAL TOTAL

MAX1470

315MHz Low-Power, +3V Superheterodyne

Receiver

_______________________________________________________________________________________ 7

MAX1470

When the crystal is loaded as specified, i.e., C

load

spec

, the frequency pulling equals zero.

Data Filter

The data filter is implemented as a 2nd-order lowpass

Sallen-Key filter. The pole locations are set by the combi-

nation of two on-chip resistors and two external capaci-

tors. Adjusting the value of the external capacitors

changes the corner frequency to optimize for different

data rates. The corner frequency should be set to

approximately 1.5 times the fastest expected data rate

from the transmitter. Keeping the corner frequency near

the data rate rejects any noise at higher frequencies,

resulting in an increase in receiver sensitivity.

The configuration shown in Figure 1 can create a

Butterworth or Bessel response. The Butterworth filter

offers a very flat amplitude response in the passband

and a roll-off rate of 40dB/decade for the two-pole filter.

The Bessel filter has a linear phase response, which

works well for filtering digital data. To calculate the

value of C5 and C6, use the following equations along

with the coefficients in Table 1:

where f

is the desired 3dB corner frequency.

For example, to choose a Butterworth filter response

with a corner frequency of 5kHz:

Choosing standard capacitor values changes C5 to

470pF and C6 to 220pF, as shown in the Typical

Application Circuit.

Data Slicer

The purpose of the data slicer is to take the analog out-

put of the data filter and convert it to a digital signal.

This is achieved by using a comparator and comparing

the analog input to a threshold voltage. The threshold

voltage is set by the voltage on DSN, which is connect-

ed to the negative input of the data slicer comparator.

The positive input is connected to the output of the data

filter internally, and also the DSP pin for use with some

data slicer configurations.

The suggested data slicer configuration uses a resistor

(R1) connected between DSN and DSP with a capaci-

tor (C4) from DSN to DGND (Figure 2). This configura-

tion averages the analog output of the filter and sets the

threshold to approximately 50% of that amplitude. With

this configuration, the threshold automatically adjusts

as the analog signal varies, minimizing the possibility

for errors in the digital data. The sizes of R1 and C4

affect how fast the threshold tracks the analog ampli-

tude. Be sure to keep the corner frequency of the RC

circuit lower than the lowest expected data rate.

Note that a long string of zeros or ones can cause the

threshold to drift. This configuration works best if a cod-

ing scheme, such as Manchester code, which has an

equal number of zeros and ones, is used.

Peak Detector

The peak detector output (PDOUT), in conjunction with

an external RC filter, creates a DC output voltage equal

to the peak value of the data signal. The resistor pro-

vides a path for the capacitor to discharge, allowing the

k kHz

1 000

1 414 100 3 14 5

450

1 414

4 100 3 14 5

225

()( )()()

≈

()( )( )( )

≈

Ω

ak f

100

4 100

()()()

Ω

315MHz Low-Power, +3V Superheterodyne

Receiver

8 _______________________________________________________________________________________

FILTER TYPE a b

Butterworth

(Q = 0.707)

1.414 1.000

Bessel

(Q = 0.577)

1.3617 0.618

Table 1. Coefficents to Calculate C5 and C6

Figure 1. Sallen-Key Lowpass Data Filter

DSP

DF2

100kΩ R

DF1

100kΩ

RSSI

OPP

MAX1470

peak detector to dynamically follow peak changes of

the data filter output voltage. For faster receiver startup,

the circuit shown in Figure 3 can be used.

433.92MHz Band

The MAX1470 can be configured to receive ASK modu-

lated data with carrier frequency ranging from 250MHz

to 500MHz. Only a small number of components need

to be changed to retune the RF section to the desired

RF frequency.

Table 2 shows a list of changed components and their

values for a 433.92MHz RF; all other components

remain unchanged.

The integrated image rejection of the MAX1470 is

specifically designed to function with a 315MHz input

frequency by attenuating any signal at 293.6MHz. The

benefit of the on-chip image rejection is that an external

SAW filter is not needed, reducing cost and the inser-

tion loss associated with SAW filters. The image rejec-

tion cannot be retuned for different RF input

frequencies and therefore is degraded. The image

rejection at 433.92MHz is typically 39dB.

Layout Considerations

A properly designed PC board is an essential part

of any RF/microwave circuit. On high-frequency inputs

and outputs, use controlled-impedance lines and

keep them as short as possible to minimize losses and

radiation. At high frequencies, trace lengths that are

approximately 1/20 the wavelength or longer become

antennas. For example, a 2in trace at 315MHz can act

as an antenna.

Keeping the traces short also reduces parasitic induc-

tance. Generally, 1in of a PC board trace adds about

20nH of parasitic inductance. The parasitic inductance

can have a dramatic effect on the effective inductance.

For example, a 0.5in trace connecting a 100nH induc-

tor adds an extra 10nH of inductance or 10%.

To reduce the parasitic inductance, use wider traces

and a solid ground or power plane below the signal

traces. Using a solid ground plane can reduce the par-

asitic inductance from approximately 20nH/in to 7nH/in.

Also, use low-inductance connections to ground on all

GND pins, and place decoupling capacitors close to all

connections.

Chip Information

TRANSISTOR COUNT: 1835

PROCESS: CMOS

MAX1470

315MHz Low-Power, +3V Superheterodyne

Receiver

_______________________________________________________________________________________ 9

COMPONENT VALUE FOR 433MHz RF

C9 1.0pF

L1 15nH

L2 56nH

Y1 6.6128MHz

Table 2. Changed Component Values for

433.92MHz

Note: These values are affected by PC board layout.

DSN

DSP

MAX1470

DATA OUT

DATA

SLICER

DATA

FILTER

47nF

25kΩ

DSN

DSP

MAX1470

DATA OUT

DATA

SLICER

DATA

FILTER

PDOUT

250kΩ

47nF

Figure 2. Generating Data Slicer Threshold Figure 3. Using PDOUT for Faster Startup

P1-P3 P4-P6 P7-P9 P10-P12

MAX1470EUI+

Mfr. #:

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Manufacturer:

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Description:

RF Receiver 315MHz Low-Power 3V Superheterodyne Rcvr

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