RT8208A/B
15
DS8208A/B-04 May 2011 www.richtek.com
POR, UVLO and Soft-Start
Power On Reset (POR) occurs when VDD rises above to
approximately 4.3V. after POR is triggered. And then, the
RT8208A/B will reset the fault latch and prepare the PWM
for operation. Below 4.1V (MIN), the VDD under voltage
lockout (UVLO) circuitry inhibits switching by keeping
UGATE and LGATE low. A built-in soft-start is used to
prevent surge current from power supply input after EN is
enabled. The maximum allowed current limit is segmented
in 4 steps: 25%, 50%, 75% and 100% during this period,
each step is 128 UGATE clks. The current limit steps can
eliminate the V
OUT
folded-back in the soft-start duration.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 25%
of the its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor. The RT8208A/B is latched once OVP is
triggered and can only be released by VDD or EN power
on reset. There is 20μs delay built into the over voltage
protection circuit to prevent false transitions.
When Gx changes state, the OVP function is masked for
32 clock cycle while VOUT and FB are changed to the
new level. After that the mask will be disabled.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. In order to remove the residual charge on
the output capacitor during the under voltage period, if
PHASE is greater than 1V, the LGATE is forced high until
PHASE is lower than 1V. There is 2.5μs delay built into
the under voltage protection circuit to prevent false
transitions. During soft-start, the UVP blanking time is
512 UGATE clks.
When Gx changes state, the UVP function is masked for
32 clock cycle while VOUT and FB change to the new
level, after which the mask is disable.
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
(
×−
×
ON IN OUT
IR LOAD(MAX)
TVV
L =
LI
Where L
IR
is the ratio of peak-to-peak ripple current to the
maximum average inductor current. Find a low-pass
inductor having the lowest possible DC resistance that
fits in the allowed dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well at 200kHz. The core must be large enough
and not to saturate at the peak inductor current (I
PEAK
) :
⎡⎤
⎛⎞
×
⎢⎥
⎜⎟
⎝⎠
⎣⎦
IR
PEAK LOAD(MAX) LOAD(MAX)
L
I = I + I
2
Output Capacitor Selection
The output filter capacitor must have low enough Equivalent
Series Resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must also be high enough to absorb the inductor energy
while transiting from full-load to no-load conditions without
tripping the overvoltage fault latch.
Although Mach Response
TM
DRV
TM
dual ramp valley mode
provides many advantages such as ease-of-use, minimum
external component configuration, and extremely short
response time, due to not employing an error amplifier in
the loop, a sufficient feedback signal needs to be provided
by an external circuit to reduce the jitter level. The required
signal level is approximately 15mV at the comparing point.
This generates V
Ripple
= (V
OUT
/ 0.75) x 15mV at the output
node. The output capacitor ESR should meet this
requirement.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
≤
××
π
SW
ESR
OUT
f
1
f =
2 ESR C 4
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
