RT8208A/B
16
DS8208A/B-04 May 2011www.richtek.com
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability.
For best performance of the RT8208A/B, the following
guidelines should be strictly followed.
` Connect an RC low pass filter from VDDP to VDD, 1μF
and 10Ω are recommended. Place the filter capacitor
close to the IC.
` Keep current limit setting network as close as possible
to the IC. Routing of the network should be kept away
from to high voltage switching nodes to prevent it from
coupling.
` Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
Figure 9. Derating Curve for RT8208A/B Package
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four Layers PCB
Large ceramic capacitors can have a high-ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting VOUT or FB divider close to
the inductor. There are two related but distinct ways
including double-pulsing and feedback loop instability to
identify the unstable operation. Double-pulsing occurs due
to noise on the output or because the ESR is too low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering a
new cycle immediately after 400ns minimum off-time
period has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased output
ripple. However, it may indicate the possible presence of
loop instability, which is caused by insufficient ESR. Loop
instability can result in oscillation at the output after line
or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit. The easiest method for stability
checking is to apply a very zero-to-max load transient
and carefully observe the output-voltage-ripple envelope
for overshoot and ringing. It helps to simultaneously monitor
the inductor current with AC probe. Do not allow more
than one ringing cycle after the initial step-response under-
or over-shoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
the RT8208A/B, the maximum junction temperature of
the die is 125°C. The junction to ambient thermal
resistance θ
JA
is layout dependent. For WQFN-16L 3x3
packages, the thermal resistance θ
JA
is 68°C/W on the
standard JEDEC 51-7 four layers thermal test board. The
maximum power dissipation at T
A
= 25°C can be calculated
by following formula :
P
D(MAX)
= (125°C − 25°C)/(68°C/W) = 1.471W for
WQFN-16L 3x3 package
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8208A/B package, the Figure 9 of
derating curve allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
