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LT3825EFE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LT3825
19
3825fe
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this
manner, hysteresis
is produced.
Referring to Figure 3, the voltage hysteresis at V
IN
is
equal to the change in bias current times R
A
. The design
procedure is to select the desired V
IN
referred voltage
hysteresis, V
UVHYS
. Then:
R
A
=
V
UVHYS
I
UVLO
where:
I
UVLO
= I
UVLOL
– I
UVLOH
is approximately 3.4µA
R
B
is then selected with the desired turn-on voltage:
R
B
=
R
A
V
IN(ON)
V
UVLO
– 1
If we wanted a V
IN
-referred trip point of 36V, with 1.8V
(5%) of hysteresis (on at 36V, off at 34.2V):
R
A
=
1.8V
3.4µA
= 529k, use 523k
R
B
=
523k
36V
1.23V
– 1
= 18.5k, use 18.7k
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 3c shows an alternate method of filtering by split-
ting the R
A
resistor with the capacitor. The split should
put more of the resistance on the UVLO side
.
Converter Start-Up
The standard topology for the LT3825 utilizes a third
transformer winding on the primary side that provides both
feedback information and local V
CC
power for the LT3825
(see Figure 4). This power “bootstrapping” improves
converter efficiency but is not inherently self-starting.
Start-up is affected with an external “trickle-charge” resis-
tor and the LT3825’s internal V
CC
undervoltage lockout
circuit
. The V
CC
undervoltage lockout has wide hysteresis
to facilitate start-up.
In operation, the “trickle charge” resistor, R
TR
, is con-
nected to V
IN
and supplies a small current, typically on the
order of 1mA to charge C
TR
. Initially the LT3825 is off and
draws only its start-up current. When C
TR
reaches the V
CC
turn-on threshold voltage the LT3825 turns on abruptly
and draws its normal supply current.
APPLICATIONS INFORMATION
V
IN
R
A
LT3825
(3a) UV Turning ON
UVLO
I
UVLO
R
B
V
IN
R
A
LT3825
(3b) UV Turning OFF (3c) UV Filtering
UVLO
UVLO
R
B
V
IN
R
A2
R
A1
C
UVLO
R
B
3825 F03
I
UVLO
Figure 3
+
I
VCC
3825 F04
R
TR
C
TR
V
IN
V
IN
I
VCC
V
VCC
V
ON
THRESHOLD
0
V
PG
V
CC
LT3825 PG
GND
•
•
•
Figure 4. Typical Power Bootstrapping
LT3825
20
3525fe
Switching action commences and the converter begins to
deliver power to the output. Initially the output voltage is low
and the flyback voltage is also low, so C
TR
supplies most
of the LT3825 current (only a fraction comes from R
TR
.)
V
CC
voltage continues to drop until after some time, typi-
cally tens of milliseconds, the output voltage approaches
its desired value. The flyback winding then
provides the
LT3825 supply current and the V
CC
voltage stabilizes.
If C
TR
is undersized, V
CC
reaches the V
CC
turn-off threshold
before stabilization and the LT3825 turns off. The V
CC
node then begins to charge back up via R
TR
to the turn-
on threshold, where the part again turns on. Depending
upon the circuit, this may result in either several on-off
cycles
before proper operation is reached, or permanent
relaxation oscillation at the V
CC
node.
R
TR
is selected to yield a worst-case minimum charging
current greater than the maximum rated LT3825 start-up
current, and a worst-case maximum charging current less
than the minimum rated LT3825 supply current.
R
TR(MAX)
<
V
IN(MIN)
– V
CC(ON _ MAX)
I
CC(ST _ MAX)
and
R
TR(MIN)
>
V
IN(MAX)
– V
CC(ON _ MIN)
I
CC(MIN)
Make C
TR
large enough to avoid the relaxation oscillatory
behavior described above. This is complicated to deter-
mine theoretically as it depends on the particulars of the
secondary circuit and load behavior. Empirical testing is
recommended. Note that the use of the optional soft-start
function lengthens the power-up timing and requires a
correspondingly larger value for C
TR
.
If you have an available input voltage
within the V
CC
range, the internal wide hysteresis range UVLO function
becomes counterproductive. In such cases it is better to
operate the LT3825 directly from the available supply. In
this case, use the LT3837 which is identical to the LT3825
except that it lacks the internal V
CC
undervoltage lockout
function. It is designed to operate directly from supplies
in the range of 4.5V to 19V
. See the LT3837 data sheet
for further information.
The LT3825 has an internal clamp on V
CC
of approximately
19.5V. This provides some protection for the part in the
event that the switcher is off (UVLO low) and the V
CC
node
is pulled high. If R
TR
is sized correctly the part should
never attain this clamp voltage.
Control Loop Compensation
Loop frequency compensation is performed
by connecting
a capacitor network from the output of the feedback ampli-
fier (V
C
pin) to ground as shown in Figure 5. Because of
the sampling behavior of the feedback amplifier, compen-
sation is different from traditional current mode switcher
controllers. Normally only C
VC
is required. R
VC
can be
used to add a “zero” but the phase margin improvement
traditionally offered by this extra resistor is usually
already
accomplished by the nonzero secondary circuit impedance.
C
VC2
can be used to add an additional high frequency pole
and is usually sized at 0.1 times C
VC
.
In further contrast to traditional current mode switchers,
V
C
pin ripple is generally not an issue with the LT3825.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
V
C
voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch-on” portion of the
next cycle. This action naturally holds the V
C
voltage stable
APPLICATIONS INFORMATION
9
R
VC
V
C
C
VC
3825 F05
C
VC2
Figure 5. V
C
Compensation Network
LT3825
21
3825fe
during the current comparator sense action (current mode
switching).
AN19 provides a method for empirically tweaking frequency
compensation. Basically it involves introducing a load
current step and monitoring the response.
Slope Compensation
This part incorporates current slope compensation. Slope
compensation is required to ensure current loop stability
when the DC is greater than 50%. In some switcher con-
trollers, slope compensation reduces the maximum peak
current at higher duty
cycles. The LT3825 eliminates this
problem by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Minimum Load Considerations
At light loads, the LT3825 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
t
ON(MIN)
resistor. If this produces more power than the
load requires, power will flow back into the primary during
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
though light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the V
C
node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds
the V
C
node voltage, the primary-side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
C
reaches its 2.56V clamp. At clamp, the primary-side
MOSFET will turn off at the rated 98mV V
SENSE
level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across R
SENSE
to exceed the max 98mV rating
because of the minimum switch-on time blanking. If the
voltage on V
SENSE
exceeds 206mV after the minimum
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V
C
capacitor. This then reduces the
peak current on the next cycle and will reduce overall
stress in the primary switch.
Short-Circuit Conditions
Loss of current limit is
possible under certain conditions
such as an output short circuit. If the duty cycle exhib-
ited by the minimum on time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
:
DC
MIN
= t
ON(MIN)
• f
OSC
<
I
SC
• R
SEC
+ R
DS(ON)
( )
V
IN
• N
SP
where:
t
ON(MIN)
= primary-side switch minimum on-time
I
SC
= short-circuit output current
NSP = secondary-to-primary turns ratio (N
SEC
/N
PRI
)
Other variables as previously defined
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher
for short-circuit protection
and adds any additional circuitry to prevent destruction.
APPLICATIONS INFORMATION
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LT3825EFE#PBF

Mfr. #:
Buy LT3825EFE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Synchronous Flyback Converter w/ no Optoisolater for Isolated Power Supplies
Lifecycle:
New from this manufacturer.
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