MGA-631P8
Low Noise, High Linearity, Active Bias Low Noise Amplier
Data Sheet
Description
Avago Technologies’ MGA-631P8 is an economical, easy-
to-use GaAs MMIC Low Noise Amplier (LNA) with active
bias. The LNA has low noise with excellent input return
loss and high linearity achieved through the use of
Avago Technologies’ proprietary 0.5um GaAs Enhance-
ment-mode pHEMT process. The LNA has an extra feature
that allows a designer to adjust supply current and gain
externally. Due to the high isolation between the input
and output, gain can be adjusted independently through
a resistor in series with a blocking capacitor from the
output pin to FB1 pin, without aecting the noise gure.
It is housed in a miniature 2.0 x 2.0 x 0.75mm
3
8-pin Thin
Small Leadless Package (TSLP) package. The compact
footprint and low prole coupled with low noise, high
gain, excellent input return loss and high linearity make
the MGA-631P8 an ideal choice as an LNA for cellular in-
frastructure for GSM, CDMA, GPS and ISM applications.
It is designed for optimum use between 400MHz to
1.5GHz. For optimum performance at higher frequency
from 1.4GHz to 3.8GHz, the MGA-632P8 is recommend-
ed. Both MGA-631P8 and MGA-632P8 share the same
package and pinout.
Pin Conguration and Package Marking
2.0 x 2.0 x 0.75 mm
3
8-lead TSLP
Features
x Low noise gure
x Good input return loss
x High linearity performance
x High Isolation
x Externally adjustable supply current, 40-80mA
x Externally adjustable gain, 15-20dB
x GaAs E-pHEMT Technology
[1]
x Low cost small package size: 2.0x2.0x0.75 mm
3
x Excellent uniformity in product specications
Specications
900MHz; 4V, 54mA (typ)
x 17.5 dB Gain
x 0.53 dB Noise Figure
x -19.4dB S11
x -34dB S12
x 32.6 dBm Output IP3
x 18.0 dBm Output Power at 1dB gain compression
Applications
x Low noise amplier for cellular infrastructure for GSM,
CDMA, GPS and ISM.
x Other ultra low noise applications.
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Bottom View
Note:
Pin 1 : not used Pin 5 : FB1
Pin 2 : RFin Pin 6 : not used
Pin 3 : RF ground Pin 7 : RFout
Pin 4 : Vbias Pin 8 : Gnd
Top View
Note:
Package marking provides
orientation and identication
“G1” is Device Code
“X” is month code
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 50 V
ESD Human Body Model = 200 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
2
MGA-631P8 Absolute Maximum Rating
[1]
Symbol Parameter Units Absolute Max.
Vd Device Supply Voltage V 5.5
P
in,max
CW RF Input Power (Vd=4.0V, Vbias=4.0V) dBm 20
P
diss
Total Power Dissipation
[2]
W 0.55
T
j
Junction Temperature °C 150
T
STG
Storage Temperature °C -65 to 150
Thermal Resistance
[3]
(Vd = 4.0V, Vbias=4.0V), θ
JC
= 47 °C/W
Notes:
1. Operation of this device in excess of any of these limits may cause permanent damage.
2. Board temperature T
B
is 25 °C. Derate 21.2mW/ °C for T
B
>124 °C.
3. Thermal resistance measured using Infra-Red Microscopy Technique.
Product Consistency Distribution Charts
[4]
4. Distribution data sample size is 500 samples taken from 3 dierent wafer lots. Future wafer allocated to this product may have nominal values
anywhere between the upper and lower limits. Circuit losses have been de-embedded from actual measurements.
Figure 3. Id distribution at 54mA
Figure 1. Gain distribution at 54mA
Figure 4. OIP3U distribution at 54mA
100
200
300
400
500
Count
31 32 33 34 35
OIP3U (dBm)
CPK Lower = 1.550
Std Dev = 0.369
LSL = 30.8
Nominal = 32.6
Process Capability for NF
NF (dB)
Frequency
0.41 0.51 0.61 0.71
0
30
60
90
120
150
CPK=4.04
Std Dev=0.04
Nominal = 0.53,
USL = 1.0
Process Capability for Gain
Gain (dB)
Frequency
16 16.5 17 17.5 18 18.5 19
0
50
100
150
200
250
300
LSL = 16.0,
Nominal = 17.5,
USL = 19.0
CPK Lower = 3.72
CPK Upper = 3.85
Std Dev = 0.13
50
100
150
200
250
Count
40 45 50 55 60 65 70
CPK Lower = 2.45
CPK = 2.68
Std Dev = 1.26
LSL = 41,
Nominal = 54,
USL=67
Id (mA)
3
Typical Electrical Specications at 700MHz
[3]
T
A
= 25 °C, Vd =4V @ 54mA, R1=91ohm unless otherwise specied.
Symbol Parameter and Test Condition Units Typ.
Gain Freq=700MHz Associated Gain dB 17.1
OIP3 Freq=700MHz Output Third Order Intercept Point
(2-tone @ F
RF
+/- 5MHz, Pin = -20dBm)
dBm 35.7
NF
50Ω
Freq=700MHz
Noise Figure in 50: system
dB 1.12
OP1dB Freq=700MHz Output Power at 1dB Gain Compression dBm 15.1
IRL Freq=700MHz Input Return Loss dB -12.1
ORL Freq=700MHz Output Return Loss dB -3.2
S12 Freq=700MHz Reverse Isolation dB -38.4
Notes:
3. Measurements obtained using demo board described in Figure 28 and Table 1, List 4. Input and output board losses have been de-embedded.
Electrical Specications
[1,2]
T
A
= 25 °C, Vd =4V @ 54mA, R1=91ohm unless otherwise specied.
Symbol Parameter and Test Condition Units Min. Typ. Max.
Id Operational Current Vbias=4.0V mA 41 54 67
Gain Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Associated Gain dB
16.0
18.4
17.9
17.5 19.0
OIP3 Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Output Third Order Intercept Point
(2-tone @ F
RF
+/- 5MHz, Pin = -20dBm)
dBm
30.8
34.2
33.8
32.6
NF
50Ω
Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Noise Figure in 50: system
dB 0.57
0.51
0.53 1.0
OP1dB Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Output Power at 1dB Gain Compression dBm 18.3
18.0
18.0
IRL Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Input Return Loss dB -20.9
-30.6
-19.4
ORL Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Output Return Loss dB -21.3
-22.1
-22.5
S12 Freq=800 MHz
Freq=850 MHz
Freq=900 MHz
Reverse Isolation dB -34.0
-34.0
-34.0
Notes:
1. Measurements obtained using demo board described in Figure 28 and Table 1, List 1. Input and output board losses have been de-embedded.
2. Guaranteed specications are 100% tested in production test circuit.

MGA-631P8-BLKG

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors GaAs RFIC LNA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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