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MPC9330AC

P1-P3P4-P6P7-P9P10-P12P13-P13
MPC9330 REVISION 8 3/11/16 10 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Figure 8. Output-to-Output Skew t
SK(O)
Figure 9. Propagation Delay (t
()
, static phase offset)
Test Reference
Figure 10. Output Duty Cycle (DC) Figure 11. I/O Jitter
T
JIT()
= |T
0
–T
1
mean|
CCLK
FB_EN
The deviation in t
0
for a controlled edge with respect to a t
0
mean
in a random sample of cycles
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
()
CCLK
FB_IN
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
SK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
V
CC
V
CC
2
GND
t
P
T
0
DC = t
P
/T
0
x 100%
Figure 12. Cycle-to-Cycle Jitter Figure 13. Period Jitter
Figure 14. Output Transition Time Test Reference
t
F
t
R
V
CC
=3.3 V
2.4
0.55
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
T
N
T
JIT(CC)
= |T
N
–T
N+1
|
T
N+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
T
JIT(PER)
= |T
N
–1/f
0
|
T
0
PACKAGE DIMENSIONS
12 REF
DIM MIN MAX
MILLIMETERS
A
A1
7.00 BSC
A2
0.80 BSC
b
9.00 BSC
b1 0.30 0.40
c 0.09 0.20
c1 0.09 0.16
D
D1
e
E
E1
L
L1
1.00 REF
R1 0.08 0.20
R2
S
1
1.40 1.60
0.05 0.15
1.35 1.45
0.30 0.45
0.08 ---
0˚ 7˚
9.00 BSC
7.00 BSC
0.50 0.70
q
q
0.20 REF
D1
D/2
EE1
1
8
9
17
25
32
D1/2
E1/2
E/2
4X
D
7
A
D
B
A-B0.20
H D
4X
A-B0.20 C D
6
6
4
4
DETAIL G
PIN 1 INDEX
DETAIL AD
R R2
θ˚
(S)
L
(L1)
0.25
GAUGE PLANE
A2
A
A1
(θ1˚)
8X
R R1
e
SEATING
PLANE
DETAIL AD
0.1 C
C
32X
28X
H
DETAIL G
F
F
e/2
A, B, D
3
SECTION F-F
BASE
c1c
b
b1
METAL
A-B
M
0.20 DC
5 8
PLATING
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC9330 REVISION 8 3/11/16 11 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
MPC9330 REVISION 8 3/11/16 12 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Revision History Sheet
Rev Table Page Description of Change Date
8 1 NRND – Not Recommend for New Designs
12/19/12
8 1 Removed NRND 5/5/15
8
1 Product Discontinuation Notice - Last time buy expires September 7, 2016.
PDN N-16-02
3/11/16
P1-P3P4-P6P7-P9P10-P12P13-P13

MPC9330AC

Mfr. #:
Buy MPC9330AC
Manufacturer:
NXP / Freescale
Description:
Clock Generators & Support Products 3.3V 200MHz Clock Generator
Lifecycle:
New from this manufacturer.
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