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MPC9330AC

P1-P3P4-P6P7-P9P10-P12P13-P13
MPC9330 REVISION 8 3/11/16 4 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table
(1)
1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1].
CLK_STOP0 CLK_STOP1 QA[0:1] QB[0:1] QC[0:1]
0 0 Active Stopped in logic L state Stopped in logic L state
0 1 Active Stopped in logic L state Active
1 0 Stopped in logic L state Stopped in logic L state Active
1 1 Active Active Active
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch-Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 10 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 5. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit
V
CC
Supply Voltage –0.3 3.9 V
V
IN
DC Input Voltage –0.3 V
CC
+0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+0.3 V
I
IN
DC Input Current 20 mA
I
OUT
DC Output Current 50 mA
T
S
Storage Temperature –65 125 °C
Table 6. DC Characteristics (V
CC
= 3.3 V 5%, T
A
= 0°C to 70°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
V
OH
Output High Voltage 2.4 V
I
OH
= -24 mA
(1)
1. The MPC9330 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
I
OL
= 12 mA
Z
OUT
Output Impedance 14 – 17
I
IN
Input Current
(2)
2. Inputs have pull-down or pull-up resistors affecting the input current.
100 A V
IN
= V
CC
or GND
I
CC_PLL
Maximum PLL Supply Current 5.0 10 mA V
CC_PLL
Pin
I
CCQ
Maximum Quiescent Supply Current 5.0 10 mA All V
CC
Pins
MPC9330 REVISION 8 3/11/16 5 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 7. AC Characteristics (V
CC
= 3.3 V 5%, T
A
= 0°C to 70°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input Reference Frequency
(2)
4 feedback
(3)
PLL mode, external feedback 8 feedback
12 feedback
16 feedback
24 feedback
PLL mode, internal feedback  16 feedback)
Input Reference Frequency in PLL bypass mode
(4)
2. PLL mode requires PLL_EN = 0 to enable the PLL.
3. 4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one 2 output to FB_IN. See Table 3 to Table 5 for
other feedback configurations.
4. In bypass mode, the MPC9330 divides the input reference clock.
50
25
16.67
12.5
8.33
12.5
120
60
40
30
20
30
TBD
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
f
VCO
VCO Lock Frequency Range
(5)
5. The input frequency f
ref
on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f
ref
= f
VCO
FB.
200 480 MHz
f
XTAL
Crystal Interface Frequency Range
(6)
6. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
10 25 MHz
f
MAX
Output Frequency 4 output
8 output
12 output
16 output
24 output
50
25
16.67
12.5
8.33
120
60
40
30
20
MHz
MHz
MHz
MHz
MHz
PLL locked
f
refDC
t
PW, MIN
Reference Input Duty Cycle
Minimum Input Reference Pulse Width
25
2
75 %
ns
t
r
, t
f
CCLK Input Rise/Fall Time 1.0 ns 0.8 to 2.0 V
t
()
Propagation Delay (SPO)
(7)
for the - entire f
ref
range
- f
ref
= 8.33 MHz
- f
ref
= 50.0 MHz
7. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked). t
sk(o)
[ps] = t
sk(o)
[°] B(fref 360°)
-1.2
-400
-70
+1.2
+400
+70
°
ps
ps
t
sk(o)
Output-to-Output Skew
(8)
(within output bank)
(any output)
8. Skew data applicable for equally loaded outputs only.
50
150
ps
ps
DC Output Duty Cycle 45 50 55 %
t
r
, t
f
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
t
PLZ, HZ
Output Disable Time 10 ns
t
PZL, LZ
Output Enable Time 10 ns
t
JIT(CC)
Cycle-to-cycle jitter 50 300 ps
t
JIT(PER)
Period Jitter 35 250 ps
t
JIT()
I/O Phase Jitter RMS (1) 10 70 ps
BW
PLL closed loop bandwidth
(9)
4 feedback
PLL mode, external feedback 8 feedback
12 feedback
16 feedback
24 feedback
9. –3 dB point of PLL transfer characteristics.
0.8-5.0
0.5-2.0
0.3-1.0
0.25-0.6
0.2-0.5
MHz
MHz
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time 10 ms
MPC9330 REVISION 8 3/11/16 6 ©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet 3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Output Power Down (PWR_DN) Timing Diagram
Output Clock Stop (CLK_STOP) Timing Diagram
Programming the MPC9330
The MPC9330 supports output clock frequencies from 8.33 to
120 MHz. Different feedback and output divider configurations can
be used to achieve the desired input to output frequency
relationship. The feedback frequency and divider should be used to
situate the VCO in the frequency lock range between 200 and 480
MHz for stable and optimal operation. The FSELA, FSELB, FSELC
and PWR_DN pins select the desired output clock frequencies.
Possible frequency ratios of the reference clock input to the outputs
are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Table 8 through Table 10
illustrate the various output configurations and frequency ratios
supported by the MPC9330.
VCO2
VCO4
PWR_DWN
QAx (2)
QBx (4)
QCx (6)
QAx (2)
QBx (4)
QCx (6)
CLK_STOP0
CLK_STOP1
QAx (2)
QBx (4)
QCx (6)
P1-P3P4-P6P7-P9P10-P12P13-P13

MPC9330AC

Mfr. #:
Buy MPC9330AC
Manufacturer:
NXP / Freescale
Description:
Clock Generators & Support Products 3.3V 200MHz Clock Generator
Lifecycle:
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