C8051F700-DK
10 Rev. 0.3
6.3. System Clock Sources
6.3.1. Internal Oscillator
The C8051F700 devices feature a calibrated internal oscillator which is enabled as the system clock source on
reset. After reset, the internal oscillator operates at a frequency of 24.5 MHz (±2%) by default, but may be
configured by software to operate at other frequencies. Therefore, in many applications an external oscillator is not
required. However, if you wish to operate the C8051F700 device at a frequency not available with the internal
oscillator, an external oscillator source may be used. Refer to the C8051F70x datasheet for more information on
configuring the system clock source.
6.3.2. External Oscillator Options
The main board is designed to facilitate the use of external clock sources. To use an external CMOS clock source,
the clock can simply be applied to P0.3. For RC and C modes, place a shorting block on header J10. To implement
the RC mode option, placeholders for an 0805-packaged capacitor (C17) and resistor (R14) are supplied on the
board. The C (capacitor) clock option can be implemented by using only the capacitor placeholder (C17). To
reduce the amount of stray capacitance on the pin, which could affect the frequency in either RC or C mode,
resistor R13 can also be removed from the board when using C or RC mode. To implement external crystal mode,
place shorting blocks at headers J9 and J10 and install the crystal at the pads marked Y1. Install a 10 M resistor
at R13 and install capacitors at C17 and C18 using values appropriate for the crystal you select. Refer to the
C8051F700 datasheet for more information on the use of external oscillators.
6.4. Switches and LEDs
Two push-button switches are provided on the main board. Switch RESET is connected to the RESET pin of the
C8051F700. Pressing RESET puts the device into its hardware-reset state. Switch SW1 P1.1 can be connected to
the C8051F700’s general purpose I/O (GPIO) pin P1.0 through header J8. Pressing Switch SW1 P1.1 generates a
logic low signal on the port pin. Remove the shorting block from the J8 header to disconnect Switch SW1 P1.1 from
the port pin.
Four capacitive sense switches are provided on the target board. The operation of these switches require
appropriate firmware running on the C8051F700 MCU that can sense the state of the switch. See Section "5.3.
Capacitive Sense Switch Example" on page 5 for details about example source code.
Three LEDs are also provided on the target board. The red LED labeled USB PWR (DS1) is used to indicate a USB
connection to P4. The red LED labeled DS2 indicates when power is being applied to the board through J15.
Finally, the green LED labeled P1.0 (DS2) can be connected to the C8051F700’s GPIO pin P1.0 through header
J8. Remove the shorting block from the header to disconnect the LED from the port pin.
See Table 1 for the port pins and headers corresponding to the switches and LEDs.
Table 1. Target Board I/O Descriptions
Description Label I/O Header
Push-button Switch SW1 P1.1 J8
Push-button Switch SW2 RESET none
Capacitive Sense Switch C1 P2.0 none
Capacitive Sense Switch C2 P2.1 none
Capacitive Sense Switch C3 P2.2 none
Capacitive Sense Switch C4 P2.3 none
Green LED DS3 P1.0 J8
Red LED DS2 VDD none
Red LED DS1 5V_VBUS none
C8051F700-DK
Rev. 0.3 11
6.5. Target Board DEBUG Interface (DEBUG / P3)
The DEBUG connector J9 provides access to the DEBUG (C2) pins of the C8051F700. It is used to connect the
Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.
Table 2 shows the DEBUG pin definitions.
Table 2. Debug Connector (P3) Description
6.6. Port I/O Connectors (J0-J6)
Each of the parallel ports of the C8051F700 has its own 10-pin header connector. Each connector provides a pin
for the corresponding port pins 0-7, VDD, and digital ground. The same pin-out is used for all of the port
connectors, and is shown in Table 3 .
6.7. Serial Interface (P4)
A USB-to-UART bridge circuit (U2) and USB connector (P4) are provided on the target board to facilitate serial
connections to UART0 of the C8051F700. The Silicon Labs CP2103 USB-to-UART bridge provides data
connectivity between the C8051F700 and the PC via a USB port. The TX and RX signals of UART0 may be
connected to the CP2102 by installing shorting blocks on header J17. The shorting block between VDD and VIO on
header J12[1-2] is required when using this interface. Optionally, firmware can use I/O pins for hardware
handshaking (/RTS and /CTS). The shorting block positions for connecting each of these signals to the CP2103
are listed in Table 4. To use this interface, the USB-to-UART device drivers should be installed as described in
Section "4.1. CP210x USB to UART VCP Driver Installation" on page 3.
Pin # Description
1 VDD_F700 (+3.3 VDC)
2, 3, 9 GND (Ground)
4C2D
5 /RST (Reset)
6 Not connected
7 /RST/C2CK
8 Not connected
10 USB Power (+5 VDC)
Table 3. Port I/O Connector Pin Description
Pin # Pin Description
1Pn.0
2Pn.1
3Pn.2
4Pn.3
5Pn.4
6Pn.5
7Pn.6
8Pn.7
9 VDD (VDD_F700)
10 GND (Ground)
C8051F700-DK
12 Rev. 0.3
6.8. Voltage Reference (VREF) and Analog Ground Connectors (J13 and J14)
The VREF connector can be used to connect the VREF pin from the MCU (P0.0) to external 0.1 uF and 4.7 uF
decoupling capacitors. The C8051F700 device is connected to the capacitors through the J13 header. The AGND
pin from the MCU (P0.1) can be connected to the board digital ground through the J14 header.
6.9. Potentiometer (J16)
The C8051F700 device has the option to connect port pin P1.2 to a 10 k linear potentiometer. The potentiometer
is connected through the J16 header. The potentiometer can be used for testing the analog-to-digital (ADC)
converter of the MCU.
6.10. C2 Pin Sharing
On the C8051F700, the debug pin C2CK is shared with the /RST pin. The target board includes the resistor
necessary to enable pin sharing which allows the pin–shared /RST to be used normally while simultaneously
debugging the device. See Application Note “AN124: Pin Sharing Techniques for the C2 Interface” at
www.silabs.com for more information regarding pin sharing.
Table 4. Serial Interface Header (J12) Description
Header Pins MCU I/O Pin CP2103 Pin
J12[1-2] none Board VDD to CP2103 VIO
J12[3-4] P0.5 TXD
J12[5-6] P0.4 RXD
J12[7-8] P0.6 /RTS
J12[9-10] P0.7 /CTS

C8051F700DK

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Development Boards & Kits - 8051 C8051F700 MCU Family Development Kit
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New from this manufacturer.
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