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IS42RM32160C-75BLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Integrated Silicon Solution, Inc. 13
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
Symbol Parameter Test Condition -7 –75 Unit
I
dd1
(1)
Operating Current One Bank Active, CL = 3, BL = 1,
tclk = tCLK(min), tRC = tRC(min)
140 130 mA
I
dd2p
(4)
Precharge Standby Current
(In Power-Down Mode)
CKE ≤ V
il (max), tCK = 15ns
CS ≥ V
dd - 0.2V
2 2 mA
I
dd2ps
(4)
Precharge Standby Current
With Clock Stop
(In Power-Down Mode)
CKE ≤ V
il (max), CLK ≤ Vil (max)
CS ≥ V
dd - 0.2V
2 2 mA
I
dd2n
(2)
Precharge Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tCK = 15 ns
50 50 mA
I
dd2ns Precharge Standby Current
With Clock Stop
(In Non-Power Down Mode)
CS ≥ V
dd - 0.2V, CKE ≥ Vih (min)
All Inputs Stable
30 30 mA
I
dd3p
(2)
Active Standby Current
(In Power-Down Mode)
CKE ≤ V
il (max), CS ≥ Vdd - 0.2V
tCK = 15 ns
5 5 mA
I
dd3ps Active Standby Current
With Clock Stop
(In Power-Down Mode)
CKE ≤ V
il (max), CLK ≤ Vil (max)
CS ≥ V
dd - 0.2V
5 5 mA
I
dd3n
(2)
Active Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tCK = 15 ns
65 65 mA
I
dd3ns Active Standby Current
With Clock Stop
(In Non Power-Down Mode)
CS ≥ V
dd - 0.2V, CKE ≥ Vih (min)
All Inputs Stable
35 35 mA
I
dd4 Operating Current All Banks Active, BL =Full, CL = 3
tCK = tCK(min)
180 170 mA
I
dd5 Auto-Refresh Current tRC = tRC(min), tCLK = tCLK(min) 260 250 mA
I
dd6 Self-Refresh Current CKE ≤ 0.2V 2.4 2.4 mA
I
dd7 Self-Refresh: CKE = LOW; tck = tck (MIN);
Address, Control, and Data bus inputs are
stable
Full Array, 85
o
C
Full Array, 45
o
C
Half Array, 85
o
C
Half Array, 45
o
C
1/4th Array, 85
o
C
1/4th Array, 45
o
C
1/8th Array, 85
o
C
1/8th Array, 45
o
C
1/16th Array, 85
o
C
1/16th Array, 45
o
C
2.4
1.6
2.0
1.3
1.6
1.1
1.4
0.9
1.2
0.8
mA
I
zz
(3,4)
Deep Power Down Current CKE ≤ 0.2V 40 40 mA
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V / 2.5V x32
Notes:
1. I
dd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25
o
C. Izz is not testsed.
4. Tested after 500ms delay.
14 Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
AC ELECTRICAL CHARACTERISTICS
(1, 2, 3)
-7 -75
Symbol Parameter Min. Max. Min. Max. Unit
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7
9.6
–
–
7.5
9.6
–
–
ns
ns
tAC3
tAC2
Access Time From CLK
CAS Latency = 3
CAS Latency = 2
–
–
5.4
7.0
–
–
5.4
7.0
ns
ns
tCHI CLK HIGH Level Width 2.5 – 2.5 – ns
tCL CLK LOW Level Width 2.5 – 2.5 – ns
tOH3
tOH2
Output Data Hold Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
–
–
2.7
2.7
–
–
ns
ns
tLZ Output LOW Impedance Time 0 – 0 – ns
tHZ Output HIGH Impedance Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
5.4
7.0
2.7
2.7
5.4
7.0
ns
tDS Input Data Setup Time
(2)
1.5 – 1.5 – ns
tDH Input Data Hold Time
(2)
1.0 – 1.0 – ns
tAS Address Setup Time
(2)
1.5 – 1.5 – ns
tAH Address Hold Time
(2)
1.0 – 1.0 – ns
tCKS CKE Setup Time
(2)
1.5 – 1.5 – ns
tCKH CKE Hold Time
(2)
1.0 – 1.0 – ns
tCS
Command Setup Time (CS, RAS,
CAS, WE, DQM)
(2)
1.5 – 1.5 – ns
tCH
Command Hold Time (CS, RAS,
CAS, WE, DQM)
(2)
1.0 – 1.0 – ns
tRC Command Period (REF to REF /
ACT to ACT)
67.5 – 67.5 – ns
tRAS Command Period (ACT to PRE) 45 100K 45 100K ns
tRP Command Period (PRE to ACT) 19 – 19 – ns
tRCD Active Command to Read/Write
Command Delay Time
19 – 19 – ns
tRRD Command Period (ACT [0] to
ACT [1])
14 – 15 – ns
tDPL Input Data to Precharge 14 – 15 – ns
Command Delay Time
tDAL Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
35 – 37.5 – ns
tMRD Mode Register Program Time 14 – 15 – ns
tDDE Power Down Exit Setup Time 7 – 7.5 – ns
tSRX Exit Self-Refresh to Active Time 80 – 80 – ns
tT Transition Time 0.3 1.2 0.3 1.2 ns
tREF Refresh Cycle Time
8K times
– 64 – 64 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
V
ih(min.) and Vil (max).
Integrated Silicon Solution, Inc. 15
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER -7 -75 UNITS
— Clock Cycle Time 7 7.5 ns
— Operating Frequency 143 133 MHz
t
cac
CAS Latency
3 3 cycle
trcd Active Command To Read/Write Com-
mand Delay Time
3 3 cycle
t
rac
RAS Latency (trcd + tcac) CAS Latency = 3
6 6 cycle
t
rc Command Period (REF to REF / ACT to
ACT)
10 9 cycle
t
ras Command Period (ACT to PRE) 7 6 cycle
trp Command Period (PRE to ACT) 3 3 cycle
t
rrd Command Period (ACT[0] to ACT [1]) 2 2 cycle
tccd Column Command Delay Time
(READ, READA, WRIT, WRITA)
1 1 cycle
t
dpl Input Data To Precharge Command Delay
Time
2 2 cycle
t
dal Input Data To Active/Refresh Command
Delay Time
(During Auto-Precharge)
5 5 cycle
trbd
Burst Stop Command To Output in HIGH-Z
Delay Time
(Write)
CAS Latency = 3
3 3 cycle
t
wbd Burst Stop Command To Input in Invalid
Delay Time
(Write)
0 0 cycle
trql
Precharge Command To Output in HIGH-Z
Delay Time
(Read)
CAS Latency = 3
3 3 cycle
t
wdl Precharge Command To Input in Invalid
Delay Time
(Write)
0 0 cycle
t
pql
Last Output To Auto-Precharge Start
Time (Read)
CAS Latency = 3
-2 -2 cycle
t
qmd DQM To Output Delay Time (Read) 2 2 cycle
t
dmd DQM To Input Delay Time (Write) 0 0 cycle
tmrd Mode Register Set To Command Delay
Time
2 2 cycle
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IS42RM32160C-75BLI

Mfr. #:
Buy IS42RM32160C-75BLI
Manufacturer:
ISSI
Description:
DRAM 512M (16Mx32) 133MHz 2.5v Mobile SDR
Lifecycle:
New from this manufacturer.
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