X40421V14I-B Datasheet X40420S14-A, X40420S14-AT1, X40420S14-B | P10-P12

May 25, 2006

Figure 7. Valid Data Changes on the SDA Bus

At power-up, the Fault Detection Register is defaulted

to all “0”. The system needs to initialize this register to

all “1” before the actual monitoring take place. In the

event of any one of the monitored sources failed. The

corresponding bits in the register will change from a

“1” to a “0” to indicate the failure. At this moment, the

system should perform a read to the register and

noted the cause of the reset. After reading the register

the system should reset the register back to all “1”

again. The state of the Fault Detection Register can be

read at any time by performing a random read at

address 0FFh, using the special preamble.

The FDR can be read by performing a random read at

0FFh address of the register at any time. Only one

byte of data is read by the register read operation.

MRF: Manual Reset Fail Bit (Volatile)

The MRF bit will set to “0” when Manual Reset input

goes active.

WDF: Watchdog Timer Fail Bit (Volatile)

The WDF bit will set to “0” when WDO goes active.

LV1F: Low V

Reset Fail Bit (Volatile)

The LV1F bit will be set to “0” when V

(V1MON) falls

below V

TRIP1

LV2F: Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to “0” when V2MON falls

below V

TRIP2

Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 7.

Serial Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 8.

Serial Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 8.

SCL

SDA

Data Stable Data Change Data Stable

X40420, X40421

May 25, 2006

Figure 8. Valid Start and Stop Conditions

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. See Figure 9.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives

the master access to any one of the words in the array.

After receipt of the Word Address Byte, the device

responds with an acknowledge, and awaits the next

eight bits of data. After receiving the 8 bits of the Data

Byte, the device again responds with an acknowledge.

The master then terminates the transfer by generating

a stop condition, at which time the device begins the

internal write cycle to the nonvolatile memory. During

this internal write cycle, the device inputs are disabled, so

the device will not respond to any requests from the mas-

ter. The SDA output is at high impedance. See Figure 12.

A write to a protected block of memory will suppress

the acknowledge bit.

Figure 9. Acknowledge Response From Receiver

SCL

SDA

Start Stop

Data Output

from Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

X40420, X40421

May 25, 2006

Figure 10. Byte Write Sequence

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page.

This means that the master can write 16 bytes to the

page starting at any location on that page. If the master

begins writing at location 10, and loads 12 bytes, then

the first 6 bytes are written to locations 10 through 15,

and the last 6 bytes are written to locations 0 through 5.

Afterwards, the address counter would point to location

6 of the page that was just written. If the master sup-

plies more than 16 bytes of data, then new data over-

writes the previous data, one byte at a time.

Figure 11. Page Write Operation

Figure 12. Writing 12 bytes to a 16-byte Page Starting at Location 10

The master terminates the Data Byte loading by issuing

a stop condition, which causes the device to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 11 for the address, acknowl-

edge, and data transfer sequence.

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Slave

Address

Byte

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1  n  16)

101 00

address

6 Bytes

n-1

6 Bytes

address

= 5

address pointer

ends here

Addr = 6

X40420, X40421

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

X40421V14I-B

Mfr. #:

Buy X40421V14I-B

Manufacturer:

Renesas / Intersil

Description:

IC VOLT MON DUAL SUP/SW 14-TSSOP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

X40421V14I-B

X40421V14I-B

Products related to this Datasheet