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X40421V14I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
19
May 25, 2006
A.C. CHARACTERISTICS
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
Symbol Parameter
400kHz
UnitMin. Max.
f
SCL
SCL Clock Frequency 400 kHz
t
IN
Pulse width Suppression Time at inputs 50 ns
t
AA
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
t
BUF
Time the bus free before start of new transmission 1.3 µs
t
LOW
Clock LOW Time 1.3 µs
t
HIGH
Clock HIGH Time 0.6 µs
t
SU:STA
Start Condition Setup Time 0.6 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0 µs
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Output Hold Time 50 ns
t
R
SDA and SCL Rise Time 20 +.1Cb
(1)
300 ns
t
F
SDA and SCL Fall Time 20 +.1Cb
(1)
300 ns
t
SU:WP
WP Setup Time 0.6 µs
t
HD:WP
WP Hold Time 0 µs
Cb Capacitive load for each bus line 400 pF
t
SU:STO
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
R
t
DH
t
AA
X40420, X40421
20
May 25, 2006
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note: (1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
Symbol Parameter Min. Typ.
(1)
Max. Unit
t
WC
(1)
Write Cycle Time 5 10 ms
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
V2MON
V2FAIL
t
R
t
F
t
RPDX
V
RVALID
LOWLINE or
V
CC
or
V
TRIPX
t
RPDX
t
RPDX
t
RPDL
t
RPDL
t
RPDL
X = 1, 2
X40420, X40421
21
May 25, 2006
RESET/RESET/MR Timings
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Note: (1) Based on characterization data.
Symbol Parameters Min. Typ. Max. Unit
t
RPD1
(1)
t
RPDL
V
TRIP1
to RESET/RESET (Power-down only)
V
TRIP1
to LOWLINE
5µs
t
LR
(1)
LOWLINE to RESET/RESET delay (Power-down only) [= t
RPD1
-t
RPDL
] 500 ns
t
RPD2
(1)
V
TRIP2
to V2FAIL 5µs
t
PURST
Power-on Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory default)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
50
(1)
200
400
(1)
800
(1)
ms
ms
ms
ms
t
F
V
CC,
V2MON
Fall Time 20 mVµs
t
R
V
CC,
V2MON
Rise Time 20 mVµs
V
RVALID
Reset Valid V
CC
1V
t
MD
MR to RESET/ RESET delay (activation only) 500 ns
t
in1
Pulse width Suppression Time for MR 50ns
t
WDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1=1, WD0=1 (factory default)
1.4
(1)
200
(1)
25
OFF
s
ms
ms
t
RST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
100 200 300 ms
t
RST2
Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms
t
RSP
Watchdog timer restart pulse width 1 µs
V
CC
V
TRIP1
RESET
RESET
t
PURST
t
PURST
t
R
t
F
t
RPD1
V
RVALID
MR
t
MD
X40420, X40421
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

X40421V14I-B

Mfr. #:
Buy X40421V14I-B
Manufacturer:
Renesas / Intersil
Description:
IC VOLT MON DUAL SUP/SW 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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