LT3641
21
3641fa
3641 F10
L2
L1
C
IN2
C
IN
C
BST
C
OUT1
C
OUT2
Figure 9. Recommended PCB Layout, FE28 Package
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during the printed circuit board (PCB) layout. Figure 9
shows the recommended component placement with
trace, ground plane and via locations. The input loop
of the high voltage channel, which is formed by the V
IN
and SW1 pins, the external catch diode (D1), the input
capacitor (C
IN
) and the ground, should be as small as
possible. These external components should be placed
on the same side of the circuit board as the LT3641, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
The boost capacitor (C
BST
) should be as close to the BST
and SW pins as possible.
The input loop of the low voltage channel is formed by
the V
IN2
pin, the input capacitor (C
IN2
) and the ground.
Place C
IN2
close to the V
IN2
and the GND pin to minimize
this loop. Place a local, unbroken ground plane below
this input loop.
Keep the FB1 and FB2 nodes small so that the ground traces
will shield them from the switching nodes. The Exposed
Pad on the bottom of the package must be soldered to
the ground so that the pad acts as a heat sink. To keep
thermal resistance low, extend the ground plane as much as
possible, and add thermal vias under and near the LT3641
to additional ground planes within the circuit board and
on the bottom side.
Sequencing Options
In most LT3641 applications, the low voltage regulator
generating OUT2 will operate from the output of the
high voltage regulator generating OUT1. In this cascade
circuit, channel 1 must start before channel 2. However,
the LT3641 provides additional fl exibility in programming
the sequencing of the outputs. Figure 10 shows several
possibilities.
Figure 10a shows the easiest option. With EN2 tied to
FB1, channel 2 will start when OUT1 is within 10% of its
regulation point.
Figure 10b shows a simple alternative. By tying EN2 to
V
IN2
, channel 2 starts as soon as its input reaches its
minimum operating voltage of 2.3V.
Figure 10c shows a circuit that handles two other com-
mon requirements. If the system requires the low voltage
output to be in regulation before the higher voltage output
(for example core voltage must appear before the I/O sup-
ply), then add a PMOS switch and drive its gate with the
PGOOD2 pin, which will go low when both channels are
in regulation. This provides a third output OUT3, which is
present only when both OUT1 and OUT2 are in regulation.
Figure 10c also takes care of a potential problem in
cascaded power supply circuits. Because channel 2 is a
switching regulator, it appears as negative impedance load
to channel 1; as OUT1 decreases, the load required to sup-
ply the input of channel 2 increases. Since the channel 1
is current limited, you must be certain that it can supply
both its own load and the power required by channel 2. The
EN2 has an accurate threshold of 1.165V, and is used to
program an undervoltage lockout for channel 2, allowing
channel 1 to supply adequate power.
