Rev 1.1, August 7, 2008 Page 5 of 12
Input High Current
IIH
VIN=VDD, Input Pins are
programmed as PD#, OE, SSON#
or FS, and no pull-up/down resister
used
-10 - 10 μA
Input Low Current
IIL
VIN=GND, Input Pins are
programmed as PD#, OE, SSON#
or FS, and no pull-up/down resister
used
-10 - 10 μA
Pull-up or Down
Resistors
RPU/D
If Programmed at pins PD#, OE,
SSON#, FS and CLKOUT
100 175 250 kΩ
Operating Supply
Current
IDD1
FIN=27MHz and all 7 clocks are
at 33MHz and CL=0
- 16 TBD mA
Operating Supply
Current
IDD2
FIN=27MHz and all 9 clocks are
at 66MHz and CL=0
- 22 TBD mA
Standby Current
ISBC PD#=GND - 90 120 μA
Output Leakage Current
IOL OE=GND at CLKOUT pins -10 - 10 μA
Programmable
Input Capacitance at
Pins 1 and 28
Cin
Cout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolution (programming steps) - 0.5 - pF
Input Capacitance
CIN2
Pins 4 and 8 if programmed as
PD#, OE, SSON or FS
- 4 6 pF
Load Capacitance
CL All CLKOUT outputs - - 15 pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDDA=VDDX= 2.5V to 3.3V+/-10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range
FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range
FIN2 External Clock 3 - 166 MHz
Output Frequency Range
FOUT1 CLKOUT, VDDO=3.3V to 2.5V 3 - 200 MHz
FOUT2 CLKOUT, VDDO=1.8V 3 - 166 MHz
FOUT3 REFCLK, crystal or resonator input 0.25 - 48 MHz
Output Duty Cycle
DC1 SSCLK 45 50 55 %
Output Duty Cycle
DC2 REFCLK , Xtal input 45 50 55 %
Output Duty Cycle
DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle
DCIN Clock Input, Pin 3 40 50 60 %
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ1 FIN=27MHz, all 7 clocks are
programmed at 66MHz, CL=15pF
- 180 TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ2 FIN=27MHz, all 9 clocks are
programmed at 66MHz, CL=15pF
- 220 TBD ps
Power Supply Ramp
Time
tPSR Time for VDD reaching minimum
specified value and monolithic
power supply ramp
0 - 12 ms
