Rev 1.1, August 7, 2008 Page 7 of 12
Output Leakage Current
IOL OE=GND at CLKOUT pins -15 - 15 μA
Programmable
Input Capacitance at
Pins 1 and 28
Cin
Cout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolution (programming steps) - 0.5 - pF
Input Capacitance
CIN2
Pins 4 and 8 if programmed as
PD#, OE, SSON or FS
- 4 6 pF
Load Capacitance
CL All CLKOUT outputs - - 15 pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDDA=VDDX= 2.5V to 3.3V+/-10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range
FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range
FIN2 External Clock 3 - 166 MHz
FOUT1 CLKOUT, VDDO=3.3V to 2.5V 3 - 200 MHz
FOUT2 CLKOUT, VDDO=1.8V 3 - 166 MHz
FOUT3 REFCLK, crystal or resonator input 0.25 - 48 MHz
Output Duty Cycle
DC1 SSCLK 45 50 55 %
Output Duty Cycle
DC2 REFCLK , Xtal input 45 50 55 %
Output Duty Cycle
DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle
DCIN Clock Input, Pin 3 40 50 60 %
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ1 FIN=27MHz, all 7 clocks are
programmed at 66MHz, CL=15pF
- 200 TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ2 FIN=27MHz, all 9 clocks are
programmed at 66MHz, CL=15pF
- 250 TBD ps
Power supply Ramp
Time
tPSR Time for VDD reaching minimum
specified value and monolithic
power supply ramp
- - 12 ms
PLL Lock Time
tPLL Time from VDD reaching minimum
specified value to valid output
frequencies at all outputs
- 7.8 9.0 ms
PD# Power-up Time
(Crystal or Clock)
tPU2 Time from PD# rising edge to valid
frequency at outputs
- 5.5 8.0 ms
Output Enable Time
tOE Time from OE falling edge to Hi-Z at
outputs
- 250 400 ns
Output Disable Time
tOD Time from OE falling edge to Hi-Z at
outputs
- 250 400 ns
Spread Percent Range
SPR-1 Center Spread +/-0.125 - +/-2.5 %
Spread Percent Range
SPR-2 Down Spread -5.0 - -0.25 %
Modulation Frequency
FMOD Programmable, 31.5 kHz standard 25 31.5 120 kHz
