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74LVC841APW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 16 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Fig 13. Package outline SSOP24.
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65 1.25
7.9
7.6
0.9
0.7
0.8
0.4
8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT340-1 MO-150
99-12-27
03-02-19
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
112
24 13
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
A
max.
2
9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 17 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Fig 14. Package outlineTSSOP24.
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
0.4
0.3
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153
99-12-27
03-02-19
0.25
0.5
0.2
w M
b
p
Z
e
112
24
13
pin 1 index
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
A
max.
1.1
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 18 of 21
Fig 15. Package outline DHVQFN24.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
SOT815-1 - - - - - - - - -
03-04-29
SOT815-1
0 2.5 5 mm
scale
b
y
y
1
C
C
AC
C
B
v
M
w
M
e
1
e
2
terminal 1
index area
terminal 1
index area
X
UNIT
A
(1)
max.
A
1
bc eE
h
Le
1
ywv
mm
1
0.05
0.00
0.30
0.18
0.5 4.5
e
2
1.50.2
2.25
1.95
D
h
4.25
3.95
0.05 0.05
y
1
0.10.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
D
(1)
5.6
5.4
E
(1)
3.6
3.4
D
E
B
A
e
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
A
A
1
c
detail X
E
h
L
D
h
2
23
11
14
13
12
1
24
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74LVC841APW,112

Mfr. #:
Buy 74LVC841APW,112
Manufacturer:
NXP Semiconductors
Description:
Latches 10BIT BUS INTERFC
Lifecycle:
New from this manufacturer.
Delivery:
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