9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 4 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Fig 4. Logic diagram
001aaa843
Q0
D0
D
LATCH
1
Q
LE
LE
OE
LE
Q1
D1
D
LATCH
2
Q
LE LE
Q2
D2
D
LATCH
3
Q
LE LE
Q3
D3
D
LATCH
4
Q
LE LE
Q4
D4
D
LATCH
5
Q
LE LE
Q5
D5
D
LATCH
6
Q
LE LE
Q6
D6
D
LATCH
7
Q
LE LE
Q7
D7
D
LATCH
8
Q
LE LE
Q8
D8
D
LATCH
9
Q
LE LE
Q9
D9
D
LATCH
10
Q
LE LE
9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 5 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for SO24 and
(T)SSOP24.
Fig 6. Pin configuration for DHVQFN24.
841
OE V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
GND LE
001aaa836
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aaa83
7
841
Transparent top view
Q9
D8
D9
Q8
D7 Q7
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
GND
LE
OE
V
CC
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terina 1
ine area
GND
1
Table 3: Pin description
Pin Symbol Description
1
OE output enable input (active LOW)
2 D0 data input
3 D1 data input
4 D2 data input
5 D3 data input
6 D4 data input
7 D5 data input
8 D6 data input
9 D7 data input
10 D8 data input
11 D9 data input
12 GND ground (0 V)
13
LE latch enable input (active LOW)
14 Q9 3-state latch output
15 Q8 3-state latch output
9397 750 13129 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 24 May 2004 6 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
8. Limiting values
16 Q7 3-state latch output
17 Q6 3-state latch output
18 Q5 3-state latch output
19 Q4 3-state latch output
20 Q3 3-state latch output
21 Q2 3-state latch output
22 Q1 3-state latch output
23 Q0 3-state latch output
24 V
CC
supply voltage
Table 3: Pin description
…continued
Pin Symbol Description
Table 4: Function table
[1]
Operating mode Input Internal
latches
Output
OE LE Dn Qn
Enable and read register
(transparent mode)
LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and
disable outputs
HLl LZ
HLhHZ
Hold L L X NC NC
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input diode current V
I
<0V - 50 mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output diode current V
O
>V
CC
or V
O
<0V - ±50 mA

74LVC841APW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Latches 10BIT BUS INTERFC
Lifecycle:
New from this manufacturer.
Delivery:
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