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DS1220Y-100+

P1-P3P4-P6P7-P9
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
4 of 9
AC ELECTRICAL CHARACTERISTICS (T
A
: See Note 10; V
CC
= 5.0V ± 10%)
PARAMETER SYM
DS1220Y-100
UNITS NOTES
MIN
MAX
Read Cycle Time
t
RC
100
ns
Access Time
t
ACC
100
ns
OE
to Output Valid
t
OE
50 ns
CE
to Output Valid
t
CO
100
ns
OE
or
CE
to Output Active
t
COE
5 ns 5
Output High-Z from Deselection
t
OD
35
ns
5
Output Hold from Address Change
t
OH
5
ns
Write Cycle Time
t
WC
100
ns
Write Pulse Width
t
WP
75
ns
3
Address Setup Time
t
AW
0
ns
Write Recovery Time
t
WR1
t
WR2
0
10
ns
ns
12
13
Output High-Z from
WE
t
ODW
35
ns
5
Output Active from
WE
t
OEW
5
ns
5
Data Setup Time
t
DS
40
ns
4
Data Hold Time
t
DH1
t
DH2
0
10
ns
ns
12
13
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
5 of 9
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
NOT RECOMMENDED FOR NEW DESIGNS DS1220Y
6 of 9
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
CE
at V
IH
before Power-Down
t
PD
0
µs
11
V
CC
Slew from V
TP
to 0V
t
F
100
µ
s
V
CC
Slew from 0V to V
TP
t
R
0
µs
CE
at V
IH
after Power-Up
t
REC
2
ms
(T
A
= +25°C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Expected Data Retention Time
t
DR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a read cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during a write cycle, the output buffers remain in a high impedance
state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
are measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
P1-P3P4-P6P7-P9

DS1220Y-100+

Mfr. #:
Buy DS1220Y-100+
Manufacturer:
Maxim Integrated
Description:
SRAM DS1220Y-100+
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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