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7.3 Errata ATmega168
The revision letter in this section refers to the revision of the ATmega168 device.
7.3.1 Rev A
Wrong values read after Erase Only operation
Part may hang in reset
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation
may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation
with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used
as intended. Thus no special considerations are needed as long as the erased location is not
read before it is programmed.
2. Part may hang in reset
Some parts may get stuck in a reset state when a reset signal is applied when the internal reset
state-machine is in a specific state. The internal reset state-machine is in this state for approxi-
mately 10 ns immediately before the part wakes up after a reset, and in a 10 ns window when
altering the system clock prescaler. The problem is most often seen during In-System Program-
ming of the device. There are theoretical possibilities of this happening also in run-mode. The
following three cases can trigger the device to get stuck in a reset-state:
- Two succeeding resets are applied where the second reset occurs in the 10ns window before
the device is out of the reset-state caused by the first reset.
- A reset is applied in a 10 ns window while the system clock prescaler value is updated by
software.
- Leaving SPI-programming mode generates an internal reset signal that can trigger this case.
The two first cases can occur during normal operating mode, while the last case occurs only dur-
ing programming of the device.
Problem Fix/Workaround
The first case can be avoided during run-mode by ensuring that only one reset source is active.
If an external reset push button is used, the reset start-up time should be selected such that the
reset line is fully debounced during the start-up time.
The second case can be avoided by not using the system clock prescaler.
The third case occurs during In-System programming only. It is most frequently seen when using
the internal RC at maximum frequency.
If the device gets stuck in the reset-state, turn power off, then on again to get the device out of
this state.
7.3.2 Rev B
No errata.
7.3.3 Rev C
No errata.
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8. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
8.1 Rev. 2545E-02/05
8.2 Rev. 2545D-07/04
8.3 Rev. 2545C-04/04
1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package
QFN/MLF”.
2. Updated ”The EEPROM Control Register – EECR” on page 19.
3. Updated ”Calibrated Internal RC Oscillator” on page 31.
4. Updated ”External Clock” on page 33.
5. Updated Table 8-1 on page 44, Table 26-3 on page 304, Table 26-1 on page 301and
Table 25-16 on page 297
6. Added ”Pin Change Interrupt Timing” on page 83
7. Updated ”8-bit Timer/Counter Block Diagram” on page 88.
8. Updated ”Store Program Memory Control and Status Register – SPMCSR” on page
259.
9. Updated ”Enter Programming Mode” on page 286.
10. Updated ”DC Characteristics” on page 299.
11. Updated ”Ordering Information” on page 14.
12. Updated ”Errata ATmega88” on page 21 and ”Errata ATmega168” on page 22.
1. Updated instructions used with WDTCSR in relevant code examples.
2. Updated Table 6-5 on page 29, Table 8-2 on page 46, Table 24-9 on page 278, and
Table 24-11 on page 279.
3. Updated ”System Clock Prescaler” on page 34.
4. Moved “Timer/Counter2 Interrupt Mask Register – TIMSK2” and
“Timer/Counter2 Interrupt Flag Register – TIFR2” to
”8-bit Timer/Counter Register Description” on page 149.
5. Updated cross-reference in ”Electrical Interconnection” on page 206.
6. Updated equation in ”Bit Rate Generator Unit” on page 211.
7. Added ”Page Size” on page 284.
8. Updated ”Serial Programming Algorithm” on page 296.
9. Updated Ordering Information for ”ATmega168” on page 16.
10. Updated ”Errata ATmega88” on page 21 and ”Errata ATmega168” on page 22.
11. Updated equation in ”Bit Rate Generator Unit” on page 211.
1. Speed Grades changed: 12MHz to 10MHz and 24MHz to 20MHz
2. Updated ”Maximum Speed vs. VCC” on page 301.
3. Updated ”Ordering Information” on page 14.
4. Updated ”Errata ATmega88” on page 21.
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ATmega48/88/168
8.4 Rev. 2545B-01/04
1. Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption
Estimates in 8.”Features” on page 1.
2. Updated ”Stack Pointer” on page 11 with RAMEND as recommended Stack Pointer
value.
3. Added section ”Power Reduction Register” on page 39 and a note regarding the use
of the PRR bits to 2-wire, Timer/Counters, USART, Analog Comparator and ADC
sections.
4. Updated ”Watchdog Timer” on page 49.
5. Updated Figure 13-2 on page 128 and Table 13-3 on page 129.
6. Extra Compare Match Interrupt OCF2B added to features in section ”8-bit
Timer/Counter2 with PWM and Asynchronous Operation” on page 138
7. Updated Table 7-2 on page 39, Table 21-5 on page 254, Table 25-4 to Table 25-7 on
page 281 to 283 and Table 21-1 on page 244. Added note 2 to Table 25-1 on page
280. Fixed typo in Table 11-1 on page 84.
8. Updated whole ”ATmega48/88/168 Typical Characteristics – Preliminary Data” on
page 307.
9. Added item 2 to 5 in ”Errata ATmega48” on page 20.
10. Renamed the following bits:
- SPMEN to SELFPRGEN
- PSR2 to PSRASY
- PSR10 to PSRSYNC
- Watchdog Reset to Watchdog System Reset
11. Updated C code examples containing old IAR syntax.
12. Updated BLBSET description in ”Store Program Memory Control and Status Register
– SPMCSR” on page 269.

ATMEGA88-20AUR

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
8-bit Microcontrollers - MCU AVR 8K FLSH 2KB EE 4KB SRAM-20MHz 5V
Lifecycle:
New from this manufacturer.
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