NLV74HC139ADTR2G

MC74HC139A
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
*55_C to 25_C 85_C 125_C
Unit
V
IH
Minimum HighLevel Input
Voltage
V
OUT
= 0.1 V or V
CC
0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum LowLevel Input
Voltage
V
OUT
= 0.1 V or V
CC
0.1 V
|I
OUT
| 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum HighLevel Output
Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
|I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum LowLevel Output
Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
|I
OUT
| 4.0 mA
|I
OUT
| 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
IN
Maximum Input Leakage
Current
V
IN
= V
CC
or GND 6.0 0.1 1.0 1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
IN
= V
CC
or GND
I
OUT
= 0 mA
6.0 4 40 160
mA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
*55_C to 25_C 85_C 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Select to Output Y
(Figures 1 and 3)
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 3)
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor HighSpeed
CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Decoder) (Note 8) 55 pF
8. Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC
2
f I
CC
V
CC
.
MC74HC139A
http://onsemi.com
5
VALID
t
THL
t
TLH
Figure 3. Switching Waveform
V
CC
GND
t
r
t
PHL
t
PLH
OUTPUT Y
SELECT
90%
50%
10%
90%
50%
10%
Figure 4. Switching Waveform
50%
t
PHL
t
PLH
V
CC
GND
OUTPUT Y
50%
INPUT A
* Includes all probe and jig capacitance
Figure 5. Test Circuit
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
f
VALID
MC74HC139A
http://onsemi.com
6
PIN DESCRIPTIONS
ADDRESS INPUTS
A0
a
, A1
a
, A0
b
, A1
b
(Pins 2, 3, 14, 13)
Address inputs. These inputs, when the respective 1of4
decoder is enabled, determine which of its four activelow
outputs is selected.
CONTROL INPUTS
Select
a
, Select
b
(Pins 1, 15)
Activelow select inputs. For a low level on this input, the
outputs for that particular decoder follow the Address
inputs. A high level on this input forces all outputs to a high
level.
OUTPUTS
Y0
a
Y3
a
, Y0
b
Y3
b
(Pins 4 7, 12, 11, 10, 9)
Activelow outputs. These outputs assume a low level
when addressed and the appropriate Select input is active.
These outputs remain high when not addressed or the
appropriate Select input is inactive.
SELECT
A0
A1
Y0
Y1
Y2
Y3
Figure 6. Expanded Logic Diagram
(1/2 of Device)

NLV74HC139ADTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers DUAL 1-OF-4 DECODER
Lifecycle:
New from this manufacturer.
Delivery:
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