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NB6L14MNG

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 5
1 Publication Order Number:
NB6L14/D
NB6L14
2.5 V/3.3 V 3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs with Internal Termination
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data
fanout buffer. The differential inputs incorporate internal 50
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14 to accept various logic standards, such as
LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The
VREF_AC reference output can be used to rebias capacitor−coupled
differential or single−ended input signals. The 1:4 fanout design was
optimized for low output skew applications.
The NB6L14 is a member of the ECLinPS MAX™ family of high
performance clock and data management products.
Features
• Input Clock Frequency > 3.0 GHz
• Input Data Rate > 2.5 Gb/s
• < 20 ps Within Device Output Skew
• 350 ps Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 700 mV Amplitude, Typical
• LVPECL Mode Operating Range: V
CC
= 2.375 V to 3.63 V with
GND = 0 V
• Internal 50 Input Termination Resistors Provided
• VREF_AC Reference Output Voltage
• −40°C to +85°C Ambient Operating Temperature
• Available in 3 mm x 3 mm 16 Pin QFN
• These are Pb−Free Devices
MARKING
DIAGRAM*
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QFN−16
MN SUFFIX
CASE 485G
NB6L
14
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
16
1
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
QD
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
IN
VT
IN
EN
VREFAC
1
NB6L14
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2
Q3 V
CC
Q0 Q0 V
CC
IN
VREF_AC
Q2
5678
16 15 14 13
12
11
10
9
1
2
3
4
Exposed Pad (EP)
Figure 2. QFN−16 Pinout
(Top View)
GND
VT
IN
Q3 EN
Q2
Q1
Q1
Figure 3. Logic Diagram
Q0
/Q0
Q1
/Q1
Q2
/Q2
Q3
/Q3
QD
IN
50
50
VT
/IN
EN
VREF_AC
CLK
Table 1. EN TRUTH TABLE
IN IN EN Q0:Q3 Q0:Q3
0
1
x
1
0
x
1
1
0
0
1
0+
1
0
1+
+ = On next negative transition of the input signal (IN).
x = Don’t care.
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 Q1 LVPECL Output
Non−inverted Differential Output. Typically Terminated with 50 Resistor to
V
CC
–2.0 V.
2 Q1 LVPECL Output
Inverted Differential Output. Typically Terminated with 50 Resistor to V
CC
– 2.0 V.
3 Q2 LVPECL Output
Non−inverted Differential Output. Typically Terminated with 50 Resistor to
V
CC
– 2.0 V.
4 Q2 LVPECL Output
Inverted Differential Output. Typically Terminated with 50 Resistor to V
CC
– 2.0 V.
5 Q3 LVPECL Output
Non−inverted Differential Output. Typically Terminated with 50 Resistor to
V
CC
– 2.0 V.
6 Q3 LVPECL Output
Inverted Differential Output. Typically Terminated with 50 Resistor to V
CC
– 2.0 V.
7 V
CC
− Positive Supply Voltage
8 EN LVTTL/LVCMOS Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 20). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
9 IN LVPECL, CML,
LVDS, HSTL
Inverted Differential Clock Input. Internal 50 Resistor to Termination Pin, VT.
10 VREF_AC Output Voltage Reference for capacitor−coupled inputs, only.
11 VT
Internal 100 center−tapped Termination Pin for IN and IN.
12 IN LVPECL, CML,
LVDS, HSTL
Non−inverted Differential Clock Input. Internal 50 Resistor to Termination Pin, VT.
13 GND − Negative Supply Voltage
14 V
CC
− Positive Supply Voltage
15 Q0 LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 Resistor to
V
CC
–2.0 V.
16 Q0 LVPECL Output
Inverted Differential Output. Typically Terminated with 50 Resistor to V
CC
–2.0 V.
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN
inputs, then the device will be susceptible to self−oscillation.
NB6L14
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3
Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 4 kV
> 100 V
Moisture Sensitivity (Note 2) QFN−16 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 4.0 V
V
Io
Positive Input/Output GND = 0 V −0.5 V v V
Io
v V
CC
+ 0.5 V 4.0 V
I
IN
Input Current
Source or Sink Current (IN/IN
)
"50 mA
I
VREF_AC
Source or Sink Current on VT Pin "2.0 mA
I
OUT
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
JA
Thermal Resistance
(Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4 °C/W
T
sol
Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P9P10-P10

NB6L14MNG

Mfr. #:
Buy NB6L14MNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:4 LVPECL FNOUT BUF
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