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DG421DY+

P1-P3P4-P6P7-P9P10-P12
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
_______________________________________________________________________________________ 7
0FF0N0FF
V
OUT
IN
Q = ∆V
OUT
x C
L
IN DEPENDENT ON SWITCH CONFIGURATION. 
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
∆V
OUT
DG421
DG423
DG425
R
g
-15V
V-
V
OUT
V+
+15V+5V
V
g
GND
V
IN
= 3V
WR
D
C
L
10nF
RS
V
L
S
IN
Figure 5. Charge Injection
_________________________________Timing Diagrams/Test Circuits (continued)
D
-15V
V-
R
L2
300Ω
V
OUT1
V+
+15V+5V
V
L
GND
V
D
= 10V 
V
D
= 10V
LOGIC
INPUT
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
C
L2
35pF
S
LOGIC
INPUT
SWITCH
OUTPUT 1
SWITCH
OUTPUT 2
0.9 x V
OUT
V
OUT1
0.9 x V
OUT
t
D
50%
3V
0V
0V
0V
V
OUT2
t
D
D
R
L
= 1000Ω
C
L
= 35pF
S
R
L1
300Ω
C
L1
35pF
RS
V
OUT2
DG423
IN
WR
Figure 4. DG423 Break-Before-Make Interval
-15V
V-
R
L
GND
WR
SIGNAL GENERATOR
+15V
V+
10nF
RS
+5V
V
L
10nF
D
S
0V or 2.4V
IN
DG421
DG423
DG425
V
S
V
D
NETWORK
ANALYZER
Figure 6 . Off-Isolation Rejection Ratio
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
8 _______________________________________________________________________________________
-15V
V-GND
WR
+15V
V+
10nF
RS
+5V
V
L
10nF
D
S
0V or 2.4V
IN
CAPACITANCE
METER
DG421
DG423
DG425
Figure 8. Drain/Source-Off Capacitance
_________________________________Timing Diagrams/Test Circuits (continued)
-15V
V-
R
L
GND
WR
NETWORK
ANALYZER
SIGNAL GENERATOR
+15V
V+
10nF
RS
+5V
50Ω
0V or 2.4V
0V or 2.4V
N.C.
V
L
10nF
D
IN
S
S
IN
DG421
DG423
DG425
D
Figure 7. Crosstalk
-15V
V-GND
WR
+15V
V+
10nF
RS
+5V
V
L
10nF
D
S
0V or 2.4V
IN
CAPACITANCE
METER
DG421
DG423
DG425
Figure 9. Drain/Source-On Capacitance
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
_______________________________________________________________________________________ 9
_____________________________________________Pin Configurations (continued)
2120
D3
S3
N.C.
S4
D4
18
17
16
15
14
WR
D1
N.C.
S1
IN1
4
5
6
7
8
V-
GND
N.C.
V
L
V+
RS
D2
N.C.
S2
IN2
319
13
9101112
DG423
DG425
PLCC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
S1
IN1
V-
GND
S3
D3
WR
D1
DG423
DG425
V
L
V+
IN2
S2
D2
RS
D4
S4
DIP
_____________________________Functional Diagrams/Truth Tables (continued)
WR
RS IN
SWITCH 1, 2
0
1
0
1
Off
On
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
DG423 TRUTH TABLE
D2
D1
CK
D
Q
TWO SPDT SWITCHES PER PACKAGE
S1
WR
IN1
IN2
RS
S2
DG423
S3
R
Q
CK
D
Q
R
Q
S4
D3
D4
SWITCH 3, 4
On
Off
D2
D1
CK
D
TWO DPST SWITCHES PER PACKAGE
S1
WR
IN1
IN2
RS
S2
DG425
S3
R
Q
CK
D
R
Q
S4
D3
D4
WR
RS
IN
SWITCH
01
0
1
Off
On
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
DG425 TRUTH TABLE
LATCH OPERATION TRUTH TABLE
WR
RS
IN
X1
X1
LATCH/SWITCH X
X
X
0
0
X
X
Latch operation transparent.
Control data latched in. 
Switches on or off as selected by last IN.
All latches reset. Switches on or off as
when IN = 0, WR = 0, RS = 1.
TOP VIEW
N.C. = No Internal Connection
P1-P3P4-P6P7-P9P10-P12

DG421DY+

Mfr. #:
Buy DG421DY+
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs Improved Low-Power, CMOS Analog Switches with Latches
Lifecycle:
New from this manufacturer.
Delivery:
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