MC74LVXT8051DTRG

MC74LVXT8051
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7
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set−Up
Enable to Analog Out
V
CC
GND
CHANNEL
SELECT
ANALOG
OUT
50%
t
PLH
t
PHL
50%
ON/OFF
6
8
16
V
CC
C
L
*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
V
CC
V
CC
GND
ANALOG
IN
ANALOG
OUT
50%
t
PLH
t
PHL
50%
ON
6
8
16
V
CC
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
8
ENABLE
V
CC
ENABLE
90%
50%
10%
t
f
t
r
V
CC
GND
ANALOG
OUT
t
PZL
ANALOG
OUT
t
PZH
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
10%
90%
t
PLZ
t
PHZ
50%
50%
ANALOG I/O
C
L
*
TEST
POINT
16
V
CC
1kW
1
2
1
2
POSITION 1 WHEN TESTING t
PHZ
AND t
PZH
POSITION 2 WHEN TESTING t
PLZ
AND t
PZL
V
IH
V
IL
MC74LVXT8051
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8
R
L
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 13. Power Dissipation Capacitance,
Test Set−Up
Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion
0
-10
-20
-30
-40
-50
- 100
1.0 2.0 3.125
FREQUENCY (kHz)
dB
-60
-70
-80
-90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
8
16
C
L
*
*Includes all probe and jig capacitance
OFF
R
L
R
L
V
IS
R
L
C
L
*
V
OS
f
in
0.1mF
ON/OFF
6
8
16
V
CC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
V
CC
A
11
V
CC
ON
6
8
16
V
CC
0.1mF
C
L
*
f
in
R
L
TO
DISTORTION
METER
*Includes all probe and jig capacitance
V
OS
V
IS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
V
CC
or GND logic levels. V
CC
being recognized as a logic
high and GND being recognized as a logic low. In this
example:
V
CC
= +5V = logic high
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltage V
CC
. The positive peak analog voltage
should not exceed V
CC
. Similarly, the negative peak analog
voltage should not go below GND. In this example, the
difference between V
CC
and GND is five volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to V
CC
or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
CC
− GND = 2 to 6 volts
When voltage transients above V
CC
and/or below GND
are anticipated on the analog channels, external Germanium
or Schottky diodes (D
x
) are recommended as shown in
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
MC74LVXT8051
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9
ANALOG
SIGNAL
Figure 15. Application Example Figure 16. External Germanium or
Schottky Clipping Diodes
a. Low Voltage Logic Level Shifting Control b. 2−Stage Logic Level Shifting Control
Figure 17. Interfacing to Low Voltage CMOS Outputs
ON
6
8
16
+5V
ANALOG
SIGNAL
+5V
0V
+5V
0V
11
10
9
TO EXTERNAL LSTTL COMPATIBLE
CIRCUITRY 0 to V
IH
DIGITAL SIGNALS
ON/OFF
8
16
V
CC
GND
D
x
V
CC
D
x
GND
D
x
V
CC
D
x
ANALOG
SIGNAL
ON/OFF
6
8
16
+3V
ANALOG
SIGNAL
+3V
GND
+3V
GND
11
10
9
1.8V - 2.5V
CIRCUITRY
ANALOG
SIGNAL
ON/OFF
6
8
16
+5V
ANALOG
SIGNAL
+5V
GND
+5V
GND
11
10
9
1.8V - 2.5V
CIRCUITRY
+5V
MC74VHCT1GT50 BUFFERS
V
CC
= 3.0V
Figure 18. Function Diagram, LVXT8051
13
X0
14
X1
15
X2
12
X3
1
X4
5
X5
2
X6
4
X7
3
X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE

MC74LVXT8051DTRG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Multiplexer Switch ICs LOG CMOS MLTIPLXR 8CHAN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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