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AK4121VF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ASAHI KASEI [AK4121]
MS0191-E-03 2004/08
- 4 -
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1)
Parameter Symbol min max Units
Power Supplies:
Core
Input Buffer
|AVSS-DVSS| (Note 1)
VDD
TVDD
' GND
0.3
0.3
4.6
6.0
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN - r10 mA
Input Voltage VIN 0.3 TVDD+0.3 V
Ambient Temperature (Power applied) Ta 40 85 qC
Storage Temperature Tstg 65 150 qC
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 2)
Parameter Symbol min typ max Units
Power Supplies: Core
Input Buffer
VDD
TVDD
3.0
VDD
3.3
5
3.6
5.5
V
V
Note 2. All voltages with respect to ground.
SRC PERFORMANCE
(Ta=40a85qC; VDD=3.0a3.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2;
unless otherwise specified.)
Parameter Symbol min typ max Units
Resolution 20 Bits
Input Sample Rate FSI 8 96 kHz
Output Sample Rate FSO 32 96 kHz
Dynamic Range (Input= 1kHz,
60dBFS, Note 3)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=32kHz/48kHz
FSO/FSI=96kHz/32kHz
Worst Case (FSO/FSI=32kHz/44.1kHz)
Dynamic Range (Input= 1kHz,
60dBFS, A-weighted, Note 3)
FSO/FSI=44.1kHz/48kHz
-
-
-
-
112
-
114
114
114
115
-
117
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
THD+N (Input= 1kHz, 0dBFS, Note 3)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=32kHz/48kHz
FSO/FSI=96kHz/32kHz
Worst Case (FSO/FSI=48kHz/8kHz)
-
-
-
-
-
113
112
113
111
-
-
-
-
-
103
dB
dB
dB
dB
dB
Ratio between Input and Output Sample Rate
(FSO/FSI, Note 4, Note 5)
FSO/FSI
0.33 6 -
Note 3. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT.
Note 4. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz
Note 5. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz.
ASAHI KASEI [AK4121]
MS0191-E-03 2004/08
- 5 -
DIGITAL FILTER
(Ta=
40
a
85
q
C; VDD=3.0
a
3.6V; TVDD=3.0~5.5V)
Parameter Symbol min typ max Units
Digital Filter
0.985 d FSO/FSI d 6.000 PB 0 0.4583FSI kHz
0.905 d FSO/FSI 0.985 PB 0 0.4167FSI kHz
0.714 d FSO/FSI 0.905 PB 0 0.3195FSI kHz
0.656 d FSO/FSI 0.714 PB 0 0.2852FSI kHz
0.536 d FSO/FSI 0.656 PB 0 0.2245FSI kHz
0.492 d FSO/FSI 0.536 PB 0 0.2003FSI kHz
0.452 d FSO/FSI 0.492 PB 0 0.1781FSI kHz
Passband 0.001dB
0.333 d FSO/FSI 0.452 PB 0 0.1092FSI kHz
0.985 d FSO/FSI d 6.000 SB 0.5417FSI kHz
0.905 d FSO/FSI 0.985 SB 0.5021FSI kHz
0.714 d FSO/FSI 0.905 SB 0.3965FSI kHz
0.656 d FSO/FSI 0.714 SB 0.3643FSI kHz
0.536 d FSO/FSI 0.656 SB 0.2974FSI kHz
0.492 d FSO/FSI 0.536 SB 0.2732FSI kHz
0.452 d FSO/FSI 0.492 SB 0.2510FSI kHz
Stopband
0.333 d FSO/FSI 0.452 SB 0.1822FSI kHz
Passband Ripple PR r0.01 dB
Stopband Attenuation SA 96 dB
Group Delay (Note 6) GD - 57.5 - 1/fs
Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is
output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit
LSB justified)
DC CHARACTERISTICS
(Ta=40a85qC; VDD=3.0~3.6V; TVDD=3.0~5.5V)
Parameter Symbol min typ max Units
Power Supply Current
Normal operation:
FSI=FSO=48kHz at Slave Mode: VDD=3.3V
FSI=FSO=96kHz at Master Mode: VDD=3.3V
: VDD=3.6V
Power down: PDN = “L” (Note 7)
10
20
10
-
-
40
100
mA
mA
mA
PA
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
0.7xVDD
-
-
-
-
0.3xVDD
V
V
High-Level Output Voltage (Iout=400PA)
Low-Level Output Voltage (Iout=400PA)
VOH
VOL
VDD-0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - -
r 10 PA
Note 7. All digital inputs including clock pins are held VSS.
ASAHI KASEI [AK4121]
MS0191-E-03 2004/08
- 6 -
SWITCHING CHARACTERISTICS
(Ta=40a85qC; VDD=3.0~3.6V; TVDD=3.0~5.5V; C
L
=20pF)
Parameter Symbol min typ max Units
Master Clock Input (MCLK)
Frequency
Duty Cycle
fCLK
dCLK
8.192
40
-
-
36.864
60
MHz
%
L/R clock for Input data (ILRCK)
Frequency
Duty Cycle
fs
Duty
8
48 50
96
52
kHz
%
L/R clock for Output data (OLRCK)
Frequency (Note 9) fs 32 96 kHz
Duty Cycle Slave Mode Duty 48 50 52 %
Master Mode Duty 50 %
Audio Interface Timing
Input
IBICK Period
IBICK Pulse Width Low
IBICK Pulse Width High
ILRCK Edge to IBICK “
n
” (Note 9)
BICK “n” to ILRCK Edge (Note 9)
SDTI Hold Time from IBICK “n”
SDTI Setup Time to IBICK “n”
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “n” (Note 9)
OBICK “n” to OLRCK Edge (Note 9)
OLRCK to SDTO (MSB)
OBICK “p” to SDTO
tBCK
tBCKL
tBCKH
tBLR
tLRB
tLRS
tBSD
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Output (Master Mode)
BICK Frequency
BICK Duty
BICK “p” to LRCK
BICK “p” to SDTO
fBCK
dBCK
tMBLR
tBSD
20
20
64fs
50
20
30
Hz
%
ns
ns
Power-down & Reset Timing
PDN Pulse Width (Note 10) tPD 150 ns
Note 8. Min is 8kHz when BYPASS=“H”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4121 must be reset by bringing PDN “L” to “H” upon power-up.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

AK4121VF

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IC SAMPLE RATE CONVERTER 24VSOP
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