OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

932SQ425AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 10
932SQ425 REV B 042312
Electrical Characteristics–REF
T
A
= 0 - 70°C; Supply Voltage V
DD /
V
DD A
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Output Impedance R
DSP
V
O
= V
DD
*(0.5) 12 55
Ω
1
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V
1
MIN @V
OH
= 1.0 V -33 mA 1
MAX @V
OH
= 3.135 V
-33 mA 1
MIN @V
OL
= 1.9 5 V
30 mA 1
MAX @ V
OL
= 0.4 V 38 mA 1
Clock High Time T
HIGH
1.5V 27.5
ns
1
Clock Low Time T
LOW
1.5V 27.5 ns
1
Edge Rate t
slewr/f
Rising/Falling edge rate 1 1.9 4 V/ns 1,2
Duty Cycle
d
t1
V
T
= 1.5 V 45 50.5 55 % 1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T
= 1.5 V
75 1000 ps
1
See "Single-ended Test Loads Page" for termination circuits
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured between 0.8V and 2.0V
Output Low Current
I
OL
Output High Current
I
OH
932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 11
932SQ425 REV B 042312
Clock AC Tolerances
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
CPU
SRC,
NS_SAS,
NS_SRC PCI DOT96 48MHz REF
100 100 100 100 100 100
ppm
50 50 500 250 350 1000
ps
-0.50% -0.50% -0.50% 0 0.00% 0.00% %
PPM tolerance
Cycle to Cycle Jitter
Spread
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00000 9.94900 9.99900 10.00000 10.00 100 10.05100 ns 1,2
133.33333 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2
SRC ,
NS_SAS,
NS_SRC
100.00000 9.94900 9.99900 10.00000 10.00100 10.05100 ns
1,2
PCI 33.33333 29.49700 29.99700 30.00000 30.00300 30.50300 ns 1,2
DOT96 96.00000 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2
48MHz 48.00000 20.4 8125 20.83125 20.83333 20.83542 21.18542 ns 1,2
REF
14.31818 69.78429 69.83429 69.84 128 69.84826 69.89826 ns 1,2
Notes
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
CPU
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
133.00 7.44930 7.49 930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2
PCI 33.25 29.49718 29.99718 30.07218 30.07519 30.07820 30.153 20 30.65320 ns 1,2
SRC 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.051 07 10.10107 ns 1,2
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro ductio n.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz.
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
CPU
932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 12
932SQ425 REV B 042312
General SMBus Serial Interface Information for 932SQ425
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
D3
(H)
D2
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

932SQ425AKLF

Mfr. #:
Buy 932SQ425AKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet