932SQ425AKLFT Datasheet 932SQ425AKLF, 932SQ425AKLFT | P1-P3

DATASHEET

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ425

IDT®

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 1

932SQ425 REV B 042312

General Description

The 932SQ425 is a reduced-pin-count main clock

synthesizer for Intel Romley-generation server platforms.

The 932SQ425 is driven with a 25 MHz crystal for

maximum performance. It generates CPU outputs of 100 or

133.33 MHz.

Recommended Application

Reduced pin-count CK420BQ

Output Features

• 3 - HCSL CPU outputs

• 3 - HCSL Non-Spread SAS/SRC outputs

• 2 - HCSL SRC outputs

• 1 - HCSL DOT96 output

• 1 - 3.3V 48M outpu

• 3 - 3.3V PCI outputs

• 1 - 3.3V 14.318M output

Features/Benefits

• 0.5% down spread capable on CPU/SRC/PCI outputs;

Lower EMI

• 56-pin MLF package; 21% space savings compared to

932SQ420 64-pin MLF

Key Specifications

• Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS <50ps

• Phase jitter: PCIe Gen2 <3ps rms

• Phase jitter: PCIe Gen3 <x1ps rms

• Phase jitter: QPI 9.6GB/s <0.2ps rms

• Phase jitter: NS-SAS <0.4ps rms using raw phase data

• Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.3

Block Diagram

Logic

X1_25

SRC(1:0)

SMBDAT

SMBCLK

CKPWRGD#/PD

IREF

100M_133M#

CPU_SRC_PCI

PLL (SS)

CPU(2:0)

Low Drift non-SS

PLL

<500ps LTJ

NS_SAS(1:0)

(

)

DOT96

PCI(2:0)

14.31818MHz

Non-SS PLL

REF14M

Test_Mode

Test_Sel

Non-SS PLL

932SQ425

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2

932SQ425 REV B 042312

Pin Configuration

932SQ425 Functionality

Spread Spectrum Control

Power Group Pin Numbers

932SQ425 Power Down Functionality

VDDXTAL

X2_ 25

X1_ 25

GNDXTAL

GND14

vREF14_ 3x/TEST_ SEL

VDD1 4

AVDD14

GND14

SMBCLK

SMBDAT

VDD CPU

CPU2T

CPU2C

56 55 54 53 52 51 50 49 48 47 46 45 44 43

GNDPCI

GNDCPU

VDDPCI

241VDDCPU

PCI2_ 2x

340

CPU1T

PCI1_ 2x

CPU1C

PCI0_ 2x

538CPU0T

GNDPCI

CPU0C

VDDPCI

7 36 GNDNS

VDD48

8 35 AVDD_NS_SAS

^48M_2x/100M_133M

9 34 NS_SAS1T

GND48

10 33 NS_SAS1C

GND96

11 32 NS_SAS0T

DOT96T

12 31 NS_SAS0C

DOT96C

13 30

GNDNS

AVDD96

14 29

VDDN S

15 16 17 18 19 20 21 22 23 24 25 26 27 28

TEST_MODE

CKPWRGD#/PD

VDDSRC

GNDSRC

SRC0C

SRC0 T

SRC1C

SRC1T

VDD SRC

AVD D_SRC

GNDSRC

IREF

NS_SRC0C

NS_SRC0T

Notes: Pins with ^ prefix have internal 120K pullup

Pins with v prefix have internal 120K pulldown.

932SQ425

100M_133M# CPU SRC PCI REF

NS_SAS

NS_SRC DOT96 USB

0133.33

1100

96.00 48.00 MHz100 33.33 14.318 100.00

SS_Enable

(B 1b 0)

CPU, SRC &

PCI

0OFF

1ON

VDD GND

49 48 14MHz PLL Analog

50 52 REF14M Output and Logic

56 53 25MHz XTAL

2,7 1,6 PCI Outputs and Logic

8 10 48MHz Output and Logic

14 11 96MHz PLL Analog, Output and Logic

17,23 18 SRC Outputs and Logic

24 25 SRC PLL Analog

29 30

Non-Spreading Differential Outpu ts & Logic

35 36 NS-SAS/SRC PLL Analog

41,45 42 CPU Outputs and Logic

MLF

Description

CKPWRGD#/PD

Differential

Outputs

Single-ended

Outputs

Single ended

Outputs w/Latch

1 HI-Z Low Hi-Z

Running

Note: Hi-Z on the differential outputs will result in both True and

Complement being low due to the termination network

932SQ425

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 3

932SQ425 REV B 042312

Pin Descriptions

PIN # PIN NAME TYPE DESCRIPTION

1 GNDPCI PWR Ground pin for PCI outputs and logic.

2 VDDPCI PWR 3.3V power for the PCI out puts and logic

3 PCI2_2x OUT 3.3V PCI clock output

4 PCI1_2x OUT 3.3V PCI clock output

5 PCI0_2x OUT 3.3V PCI clock output

6 GNDPCI PWR Ground pin for PCI outputs and logic.

7 VDDPCI PWR 3.3V power for the PCI out puts and logic

8 VDD48 PWR 3.3V power for the 48MHz output and logic

9 ^48M_2x/100M_133M# I/O

3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for

thresholds. This pin has a weak (~120Kom) internal pull up.

1 = 100MHz, 0 = 133MHz o

eratin

fre

uenc

10 GND48 PWR Ground pin for 48MHz output and logic.

11 GND96 PWR Ground

in for DOT96 out

ut and lo

ic.

12 DOT96T OUT

True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs

and external 33 ohm series resistors and 49.9 ohm shunt resistors are re

uired for termination.

13 DOT96C OUT

Complementary clock of different ial 96MHz output. These are current mode outputs and external 33 ohm

series resistors and 49.9 ohm shunt resistors are re

uired for termination.

14 AVDD96 PWR 3.3V

ower for the 48/96MHz PLL and the 96MHz out

ut and lo

15 TEST_MODE IN

TEST_M ODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer t o

Test Clarification Table.

16 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an

asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs

are sto

ed.

17 VDDSRC PWR 3.3V

ower for the SRC out

uts and lo

18 GNDSRC PWR Ground

in for SRC out

uts and lo

ic.

19 SRC0C OUT

Complementary clock of differential SRC output. The se are current mode outputs and extern al 33 ohm

series resistors and 49.9 ohm shunt resistors are re

uired for termination.

20 SRC0T OUT

True clock of differential SRC output. These are current mode outputs. These are current mode outputs and

external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

21 SRC1C OUT

Complementary clock of different ial SRC output. These are current mode outputs and external 33 ohm

series resistors and 49.9 ohm shunt resistors are re

uired for termination.

22 SRC1T OUT

True clock of differential SRC output. These are current mode outputs. These are current mode outputs and

external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

23 VDDSRC PWR 3.3V power for the SRC outputs and logic

24 AVDD_SRC PWR 3.3V power for the SRC PLL an alog circuits

25 GNDSRC PWR Ground pin for SRC outputs and logic.

26 IR EF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a

fixed precision resistor tied to ground in order to establish the approp riate curren t. 475 ohms is the standard

value.

27 NS_SRC0C OUT

Complementary clock of different ial non-spreading SRC output. These are current mode outputs and external

33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

28 NS_SRC0T OUT

True clock of differential non-spreading SRC output. These are current mode outputs. These are current

mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are req uired for termination.

29 VDDNS PWR 3.3V power fo r the Non-Spreading dif ferential outputs outputs and logic

30 GNDNS PWR Ground pin for non-spreading differential outputs and logic.

31 NS_SAS0C OUT

Complementary clock of different ia non-spreading SAS output. These are current mode outputs and external

33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

32 NS_SAS0T OUT

True clock of differential non-spreading SAS output. These are current mode outputs. These are current

mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are req uired for termination.

33 NS_SAS1C OUT

Complementary clock of different ial non-spreading SAS output. These are current mode outputs and external

33 ohm series resistors and 49.9 ohm shunt resistors are re

uired for termination.

34 NS_SAS1T OUT

True clock of differential non-spreading SAS output. These are current mode outputs. These are current

mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are req uired for termination.

35 AVDD_NS_SAS PWR 3.3V

ower for the non-s

readin

SAS/SRC PLL analo

circuits.

36 GNDNS PWR Ground

in for non-s

readin

differential out

uts and lo

ic.

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932SQ425AKLFT

Mfr. #:

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Manufacturer:

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Description:

Clock Synthesizer / Jitter Cleaner CK420BQ

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932SQ425AKLFT

932SQ425AKLFT

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