932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 4
932SQ425 REV B 042312
Pin Descriptions (cont.)
37 CPU0C OUT
Complementary clock of different ial CPU output. These are current mode outputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are re
q
uired for termination.
38 CPU0T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are re
q
uired for termination.
39 CPU1C OUT
Complementary clock of different ial CPU output. These are current mode outputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are required for termination.
40 CPU1T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are required for termination.
41 VDDCPU PWR 3.3V power fo r the CPU outputs and logic
42 GNDCPU PWR Ground pin for CPU outputs and logic.
43 CPU2C OUT
Complementary clock of different ial CPU output. These are current mode outputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are required for termination.
44 CPU2T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are required for termination.
45 VDDCPU PWR 3.3V power fo r the CPU outputs and logic
46 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
47 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
48 GND14 PWR Ground pin for 14MHz output and logic.
49 AVDD14 PWR Analog power pin for 14MHz PLL
50 VDD14 PWR Power pin for 14MH z output and logic
51 vREF14_3x/TEST_SEL I/O
14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.
Refer to Test Clarification Table. This
p
in has a weak
(
~120Kohm
)
internal
p
ull down.
52 GND14 PWR Ground
p
in for 14MHz out
p
ut and lo
g
ic.
53 GNDXTAL PWR Ground
p
in for Cr
y
stal Oscillator.
54 X1_25 IN Cr
y
stal in
p
ut, Nominall
y
25.00MHz.
55 X2_25 OUT C r
y
stal out
p
ut, Nominall
y
25.00MHz.
56 VDDXTAL PWR 3.3V power for the crystal oscillator.
932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 5
932SQ425 REV B 042312
Test Loads and Recommended Terminations
Differential Zo
Rp Rp
HCSL Output
Buffer
932SQ4xx Differential Test Loads
Rs
Rs
2pF 2pF
Test Load
CL=5pF
Rs
Zo
Single-ended
Output
Rs
Zo
Rs
Zo
Single-ended
Output
``
CL=5pF
CL=5pF
When driving more than one load, each load trace must be equal in length.
5 inches
5 inches
5 inches
Rs
Zo
Rs
Zo
Single-ended
Output
``
CL=5pF
CL=5pF
5 inches
5 inches
Rs
Zo
CL=5pF
5 inches
Single-ended Output Termination Table
Outp ut Load
s
Zo = 50
Zo =60
PCI/ USB 1 36 43
PCI/ USB 2 22 33
REF 1 39 47
REF 2 27 36
REF 3 10 20
Rs Value
(for each load)
Differential Output Termination Table
DIF Zo (
)Iref (
)Rs (
)Rp (
)
100 475 33 50
85 412 27 42.2 or 43.2
932SQ425
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 6
932SQ425 REV B 042312
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 932SQ425. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Current Consumption
DC Electrical Characteristics–Differential Current Mode Outputs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GN D-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0. 5V V
1
Input High Voltage V
IH SMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
O
p
era tion under these conditions is neither im
p
lied nor
g
uaranteed.
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current
I
DD3.3OP
All outputs active @100MHz, C
L
= Full load;
330 350 mA 1
Powerdown Current
I
DD3.3PD Z
All differential pairs tri-stated 16 20 mA
1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro ductio n.
T
A
= T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1 2.4 4
V/ns
1, 2, 3
Slew rate matching
Δ
Trf
Slew rate matching, Scope
avera
g
in
g
on
920
%
1, 2, 4
Voltage High VHigh 660 7 72 850 1
Voltage Low VLow -150 9 150 1
Max Voltage Vmax 810 1150 1, 7
Min Voltage Vmin -300 -17 1, 7
Vswing Vswing Scope averaging off 300 1446 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 351 550 mV 1, 5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 24 140 mV 1, 6
2
Measured from differential waveform
7
Includes overshoot and unde rshoot.
Measurement on single end ed
signal using absolute value .
mV
Statistical measurement on
single-ended signal using
oscilloscope math function.
(
Sco
p
e avera
g
in
g
on
)
mV
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute
)
allowed. The intent is to limit Vcross induced modulation b
y
settin
g
V_cross_de lta to be smaller than V_cross absolute.
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
=
2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
(100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. Th is results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).

932SQ425AKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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