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DS1086U-266+

P1-P3P4-P6P7-P9P10-P12P13-P15
DS1086
Spread-Spectrum EconOscillator
10 ______________________________________________________________________________________
ADDR Register
The A0, A1, A2 bits determine the 2-wire slave address.
The WC bit determines if the EEPROM is to be written
to after register contents have been changed. If
WC = 0 (default), EEPROM is written automatically after
a WRITE EE command. If WC = 1, the EEPROM is only
written when the WRITE EE command is issued. In
applications where the register contents are frequently
written, the WC bit should be set to 1. Otherwise, it is
necessary to wait for an EEPROM write cycle to com-
plete between writing to the registers. This also pre-
vents wearing out the EEPROM. Regardless of the
value of the WC bit, the value of the ADDR register is
always written immediately to EEPROM. When the
WRITE EE command has been received, the contents
of the registers are written into the EEPROM, thus lock-
ing in the register settings.
RANGE Register
This read-only register contains a copy of the factory-
set offset (OS). This value can be read to determine the
default value of the OFFSET register when program-
ming a new master oscillator frequency.
WRITE EE Command
This command is used to write data from RAM to
EEPROM when the WC bit in ADDR register is 1. See
the
ADDR Register
section for more details.
Example Frequency Calculations
Example #1:
Calculate the register values needed to
generate a desired output frequency of 11.0592MHz.
Since the desired frequency is not within the valid mas-
ter oscillator range of 66MHz to 133MHz, the prescaler
must be used. Valid prescaler values are 2
x
where x
equals 0 to 8 (and x is the value that is programmed
into the P3 to P0 bits of the PRESCALER register).
Equation 1 shows the relationship between the desired
frequency, the master oscillator frequency, and the
prescaler.
By trial and error, x is incremented from 0 to 8 in
Equation 2, finding values of x that yield master oscilla-
tor frequencies within the range of 66MHz to 133MHz.
Equation 2 shows that a prescaler of 8 (x = 3) and a
master oscillator frequency of 88.4736MHz generates
our desired frequency. In terms of the device register, x
= 3 is programmed in the lower four bits of the
PRESCALER register. Writing 03h to the PRESCALER
register sets the PRESCALER to 8 (and 4% peak
dither). Be aware that the J0 bit also resides in the
PRESCALER register.
f
MASTER OSCILLATOR
= f
DESIRED
x prescaler = f
DESIRED
x 2
X
f
MASTER OSCILLATOR = 11.0592MHz x 2
3
= 88.4736MHz
Once the target master oscillator frequency has been
calculated, the value of offset can be determined.
Using Table 2, 88.4736MHz falls within both OS - 1 and
OS - 2. However, choosing OS - 1 would be a poor
choice since 88.4736MHz is so close to OS - 1’s mini-
mum frequency. On the other hand, OS - 2 is ideal
since 88.4736MHz is very close to the center of
OS - 2’s frequency span. Before the OFFSET register
can be programmed, the default value of offset (OS)
f
f
prescaler
f
DESIRED
MASTER OSCILLATOR
MASTER OSCILLATOR
X
=
=
2
(2)
(3)
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12 678 9 12 893–7
Figure 4. 2-Wire Data Transfer Protocol
DS1086
Spread-Spectrum EconOscillator
______________________________________________________________________________________ 11
must be read from the RANGE register (last five bits). In
this example, 12h (18 decimal) was read from the
RANGE register. OS - 2 for this case is 10h (16 deci-
mal). This is the value that is written to the OFFSET reg-
ister.
Finally, the two-byte DAC value needs to be deter-
mined. Since OS - 2 only sets the range of frequencies,
the DAC selects one frequency within that range as
shown in Equation 3.
f
MASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET
RANGE) + (DAC value x 10kHz)
Valid values of DAC are 0 to 1023 (decimal) and 10kHz
is the step size. Equation 4 is derived from rearranging
Equation 3 and solving for DAC.
Since the two-byte DAC register is left justified, 655 is
converted to hex (028Fh) and bit-wise shifted left six
places. The value to be programmed into the DAC reg-
ister is A3C0h.
In summary, the DS1086 is programmed as follows:
PRESCALER = 03h (4% peak dither) or 13h (2% peak
dither)
OFFSET = OS - 2 or 10h (if range was read as 12h)
DAC = A3C0h
Notice that the DAC value was rounded. Unfortunately,
this means that some error is introduced. In order to
calculate how much error, a combination of Equation 1
and Equation 3 is used to calculate the expected out-
put frequency. See Equation 5.
The expected output frequency is not exactly equal to the
desired frequency of 11.0592MHz. The difference is
450Hz. In terms of percentage, Equation 6 shows that the
expected error is 0.004%. The expected error assumes
typical values and does not include deviations from the
typical as specified in the electrical tables.
Example #2:
Calculate the register values needed to
generate a desired output frequency of 100MHz.
Since the desired frequency is already within the valid
master oscillator frequency range, the prescaler is set
to divide by 1, and hence, PRESCALER = 00h (for 4%
peak dither) or 10h (for 2% peak dither).
f
MASTER OSCILLATOR
= 100.0MHz x 2
0
= 100.0MHz
Next, looking at Table 2, OS + 1 provides a range of
frequencies centered around the desired frequency. In
order to determine what value to write to the OFFSET
register, the RANGE register must first be read.
Assuming 12h was read in this example, 13h (OS + 1)
is written to the OFFSET register.
Finally, the DAC value is calculated as shown in
Equation 8.
The result is then converted to hex (0110h) and then
left-shifted, resulting in 4400h to be programmed into
the DAC register.
In summary, the DS1086 is programmed as follows:
PRESCALER = 00h (4% peak dither) or 10h (2% peak
dither)
OFFSET = OS + 1 or 13h (if RANGE was read as 12h)
DAC = 4400h
f
MHz kHz
MHz
MHz
OUTPUT
(. ) ( )
.
.
=
+×
=
=
97 28 272 10
2
100 0
1
100 0
0
DAC VALUE
MHz MHz
kHz STEP SIZE
decimal
(. . )
. ( )=
−
=
100 0 97 28
10
272 00
%
%
. .
.
.
.%
ERROR
ff
f
ERROR
MHz MHz
MHz
Hz
MHz
EXPECTED
DESIRED EXPECTED
DESIRED
EXPECTED
=
−
×
=
−
×= ×=
100
11 0592 11 05875
11 0592
100
450
11 0592
100 0 004
f
MIN FREQUENCY OF SELECTED OFFSET
RANGE DAC VALUE x kHz STEP SIZE
prescaler
f
MHz x kHz
MHz
MHz
OUTPUT
OUTPUT
(
) ( )
(. ) ( )
.
.
=
+
=
+
=
=
10
81 92 655 10
8
88 47
8
11 05875
DAC VALUE
f
MIN FREQUENCY OF SELECTED
OFFSET RANGE
kHz STEP SIZE
DAC VALUE
MHz MHz
kHz STEP SIZE
decimal
MASTER OSCILLATOR
(
)
(. . )
. ( )
=
−
=
−
=≈
10
88 4736 81 92
10
655 36 655
(4)
(8)
(7)
(6)
(5)
(9)
DS1086
Spread-Spectrum EconOscillator
12 ______________________________________________________________________________________
Since the expected output frequency is equal to the
desired frequency, the calculated error is 0%.
_______2-Wire Serial Port Operation
2-WIRE SERIAL DATA BUS
The DS1086 communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a "master." The devices that are controlled by the
master are "slaves." A master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions must control the
bus. The DS1086 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see
Figures 4 and 6):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high are
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the HIGH period of the clock sig-
nal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock
pulse per bit of data.
SDA
SCL
t
HD:STA
t
LOW
t
HIGH
t
R
t
F
t
BUF
t
HD:DAT
t
SU:DAT
REPEATED
START
t
SU:STA
t
HD:STA
t
SU:STO
t
SP
STOP START
Figure 6. 2-Wire AC Characteristics
MSB
DEVICE
IDENTIFIER
DEVICE
ADDRESS
READ/WRITE BIT
1 0 1 1 A2 A1 A0 R/W
LSB
Figure 5. Slave Address
P1-P3P4-P6P7-P9P10-P12P13-P15

DS1086U-266+

Mfr. #:
Buy DS1086U-266+
Manufacturer:
Maxim Integrated
Description:
Clock Generators & Support Products 5V Spread-Spectrum EconOscillator
Lifecycle:
New from this manufacturer.
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