Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP con-
ditions is not limited, and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
Within the bus specifications a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1086 works in both modes.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the byte has been received. The master device
must generate an extra clock pulse that is associated
with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge-related clock pulse. Of course,
setup and hold times must be taken into account. When
the DS1086 EEPROM is being written to, it is not able to
perform additional responses. In this case, the slave
DS1086 sends a not acknowledge to any data transfer
request made by the master. It resumes normal opera-
tion when the EEPROM operation is complete.
A master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Figures 4, 5, 6, and 7 detail how data transfer is
accomplished on the 2-wire bus. Depending upon the
state of the R/W bit, two types of data transfer are pos-
sible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a not acknowledge is
returned.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus is
not released.
The DS1086 can operate in the following two modes:
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START
and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is per-
formed by hardware after reception of the slave
address and direction bit.
Slave transmitter mode: The first byte is received and
handled as in the slave receiver mode. However, in this
mode, the direction bit indicates that the transfer direc-
tion is reversed. Serial data is transmitted on SDA by
the DS1086 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Slave Address
Figure 5 shows the first byte sent to the device. It
includes the device identifier, device address, and the
R/W bit. The device address is determined by the
ADDR register.
Registers/Commands
See Table 1 for the complete list of registers/com-
mands and Figure 7 for an example of using them.
__________Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1086,
decouple the power supply with 0.01µF and 0.1µF
high-quality, ceramic, surface-mount capacitors.
Surface-mount components minimize lead inductance,
which improves performance, and ceramic capacitors
tend to have adequate high-frequency response for
decoupling applications. These capacitors should be
placed as close to pins 3 and 4 as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating when they are not
used. If the DS1086 never needs to be programmed in-
circuit, including during production testing, SDA and
SCL can be tied high. The SPRD pin must be tied either
high or low.
DS1086
Spread-Spectrum EconOscillator
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