DS1086Z-450+T Datasheet DS1086U-266+, DS1086U+, DS1086Z-450+T | P7-P9

DS1086

Spread-Spectrum EconOscillator

_______________________________________________________________________________________ 7

Pin Description

PIN NAME FUNCTION

1 OUT Oscillator Output

2 SPRD Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.

Power Supply

4 GND Ground

5OE

Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is

disabled but the master oscillator is still on.

6 PDN

Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master

oscillator is disabled (power-down mode).

7 SDA

2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain

and can be wire-OR’ed with other open-drain or open-collector interfaces.

8 SCL

2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out

on falling edges.

DITHERED 260kHz TO

133MHz OUTPUT

DECOUPLING CAPACITORS

(0.1µF and 0.01µF)

SPRD

OUT

4.7kΩ 4.7kΩ

2-WIRE

INTERFACE

GND

SCL

SDA

PDN

DS1086

Processor-Controlled Mode

XTL1/OSC1

MICRO-

PROCESSOR

XTL2/OSC2

DITHERED 260kHz TO

133MHz OUTPUT

DECOUPLING CAPACITORS

(0.1µF and 0.01µF)

*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS

TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.

SPRD

OUT

GND

N.C.

SCL*

SDA*

PDN

DS1086

Stand-Alone Mode

CLOCK SPECTRUM COMPARISON

(9kHz BW, PEAK DETECT)

DS1086 fig01

FREQUENCY (MHz)

RELATIVE AMPLITUDE (dBm)

9491 9392

-35

-30

-25

-20

-15

-10

-5

-40

90 95

DS1086 NO DITHER

DS1086 4% DITHER

CRYSTAL OSC

Figure 1. Clock Spectrum Dither Comparison

MAXIMUM TEMPERATURE VARIATION

vs. MASTER FREQUENCY

FREQUENCY (MHz)

FREQUENCY % CHANGE FROM 25°C

82.75 116.2599.50

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

-2.0

66.00 133.00

DS1086 fig02

Figure 2. Temperature Variation Over Frequency

DS1086

Spread-Spectrum EconOscillator

8 _______________________________________________________________________________________

Detailed Description

A block diagram of the DS1086 is shown in Figure 3.

The internal master oscillator generates a square wave

with a 66MHz to 133MHz frequency range. The fre-

quency of the master oscillator can be programmed

with the DAC register over a two-to-one range in 10kHz

steps. The master oscillator range is larger than the

range possible with the DAC step size, so the OFFSET

over which the DAC spans. The prescaler can then be

set to divide the master oscillator frequency by 2

(where x equals 0 to 8) before routing the signal to the

output (OUT) pin.

A programmable triangle-wave generator injects an off-

set element into the master oscillator to dither its output

2% or 4%. The dither is controlled by the J0 bit in the

PRESCALER register and enabled with the SPRD pin.

The maximum spectral attenuation occurs when the

prescaler is set to 1. The spectral attenuation is

reduced by 2.7dB for every factor of 2 that is used in

the prescaler. This happens because the prescaler’s

divider function tends to average the dither in creating

the lower frequency. However, the most stringent spec-

tral emission limits are imposed on the higher frequen-

cies where the prescaler is set to a low divider ratio.

The external control input, OE, gates the clock output

buffer. The PDN pin disables the master oscillator and

turns off the clock output for power-sensitive applica-

tions*. On power-up, the clock output is disabled until

power is stable and the master oscillator has generated

512 clock cycles. Both controls feature a synchronous

enable that ensures there are no output glitches when

the output is enabled, and a constant time interval (for a

given frequency setting) from an enable signal to the

first output transition.

The control registers are programmed through a 2-wire

interface and are used to determine the output frequen-

cy and settings. Once programmed into EEPROM,

since the register settings are NV, the settings only

need to be reprogrammed if it is desired to reconfigure

the device.

OFFSET FREQUENCY RANGE (MHz)

OS - 6 61.44 to 71.67

OS - 5 66.56 to 76.79

OS - 4 71.68 to 81.91

OS - 3 76.80 to 87.03

OS - 2 81.92 to 92.15

OS - 1 87.04 to 97.27

OS* 92.16 to 102.39

OS + 1 97.28 to 107.51

OS + 2 102.40 to 112.63

OS + 3 107.52 to 117.75

OS + 4 112.64 to 122.87

OS + 5 117.76 to 127.99

OS + 6 122.88 to 133.11

Factory default setting. OS is the integer value of the 5 LSBs

of the RANGE register.

FACTORY

DEFAULT

ACCESS

PRESCALER 02h X

J0 P3 P2 P1 P0 11100000b R/W

DAC HIGH 08h b9 b8 b7 b6 b5 b4 b3 b2 01111101b R/W

DAC LOW 09h b1 b0 X

00000000b R/W

OFFSET 0Eh X

b4 b3 b2 b1 b0 1 1 1 - - - - - b R/W

ADDR 0Dh X

WC A2 A1 A0 11110000b R/W

RANGE 37h X

b4 b3 b2 b1 b0 x x x - - - - - b R

WRITE EE 3Fh NO DATA

——

Table 1. Register Summary

= Don’t care, reads as zero.

= Don’t care, reads as one.

= Don’t care, reads indeterminate.

X = Don’t care.

Table 2. Offset Settings

The power-down command must persist for at least two out-

put frequency cycles plus 10µs for deglitching purposes.

DS1086

Spread-Spectrum EconOscillator

_______________________________________________________________________________________ 9

The output frequency is determined by the following

equation:

where:

min frequency of selected OFFSET range

is the

lowest frequency (shown in Table 2 for the correspond-

ing offset).

DAC value

is the value of the DAC register (0 to 1023).

Prescaler

is the value of 2

where x = 0 to 8.

See the

Example Frequency Calculations

section for a

more in-depth look at using the registers.

________________Register Definitions

The DS1086 registers are used to determine the output

frequency and dither amount. A summary of the regis-

ters is shown in Table 1. Using the default register set-

tings below, the default output frequency is 97.1MHz.

See the

Example Frequency Calculations

section for an

example on how to determine the register settings for a

desired output frequency.

PRESCALER Register

The PRESCALER register controls the prescaler (bits P3

to P0) and dither (bit J0). The prescaler divides the mas-

ter oscillator frequency by 2

where x can be from 0 to 8.

Any prescaler value entered that is greater than 8

decodes as 8. The dither applied to the output is con-

trolled with bit J0. When J0 is high, 2% peak dither is

selected. When J0 is low, 4% peak dither is selected.

DAC HIGH/DAC LOW Register

The 2-byte DAC register sets the frequency of the master

oscillator to a particular value within the current offset

range. Each step of the DAC changes the master oscilla-

tor frequency by 10kHz. The first byte is the MSB (DAC

HIGH) and the second byte is the LSB (DAC LOW).

OFFSET Register

The OFFSET register determines the range of frequencies

that can be obtained for a given DAC setting. The factory

default offset is copied into the RANGE register so the

user can access the default offset after making changes

to the OFFSET register. See Table 2 for OFFSET ranges.

Correct operation of the device is not guaranteed out-

side the range 66MHz to 133MHz.

OUTPUT

MIN FREQUENCY OF SELECTED OFFSET RANGE

DAC VALUE kHz STEP SIZE

PRESCALER

( )

+×10

SDA

SCL

2-WIRE

INTERFACE

DAC

OFFSET

EEPROM CONTROL

REGISTERS

PRESCALER

ADDR

RANGE

SPRD

PDN

OUT

DAC

TRIANGLE WAVE

GENERATOR

VOLTAGE-CONTROLLED

OSCILLATOR

PRESCALER

BY 1, 2, 4...256

GND

MASTER

OSCILLATOR

OUTPUT

DITHER SIGNAL

DITHER

CONTROL

FREQUENCY

CONTROL VOLTAGE

DS1086

Figure 3. DS1086 Block Diagram

(1)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

DS1086Z-450+T

Mfr. #:

Buy DS1086Z-450+T

Manufacturer:

Maxim Integrated

Description:

Programmable Oscillators 5V Spread-Spectrum EconOscillator

Lifecycle:

New from this manufacturer.

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DS1086Z-450+T

DS1086Z-450+T

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