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74ABT573CSJX

P1-P3P4-P6P7-P9P10-P12P13-P13
74ABT573 — Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT573 Rev. 1.5.0
December 2007
74ABT573
Octal D-Type Latch with 3-STATE Outputs
Features
■
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■
Useful as input or output port for microprocessors
■
Functionally identical to ABT373
■
3-STATE outputs for bus interfacing
■
Output sink capability of 64mA, source capability of
32mA
■
Guaranteed output skew
■
Guaranteed multiple output switching specifications
■
Output switching specified for both 50pF and 250pF
loads
■
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■
Guaranteed latchup protection
■
High-impedance, glitch-free bus loading during entire
power up and power down
■
Nondestructive, hot insertion capability
General Description
The ABT573 is an octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable
(OE
) inputs.
This device is functionally identical to the ABT373 but
has broadside pinouts.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74ABT573CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
74ABT573CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
74ABT573CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT573 Rev. 1.5.0 2
74ABT573 — Octal D-Type Latch with 3-STATE Outputs
Connection Diagram
Pin Descriptions
Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE
) input. When OE is
LOW, the buffers are in the bi-state mode. When OE
is
HIGH the buffers are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
O
0
=
Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Pin Names Descriptions
D
0
–D
7
Data Inputs
LE Latch Enable Input (Active HIGH)
OE
3-STATE Output Enable Input
(Active LOW)
O
0
–O
7
3-STATE Latch Outputs
Inputs Outputs
OE LE D O
LHH H
LHL L
LLX O
0
HXX Z
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT573 Rev. 1.5.0 3
74ABT573 — Octal D-Type Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
T
STG
Storage Temperature –65°C to +150°C
T
A
Ambient Temperature Under Bias –55°C to +125°C
T
J
Junction Temperature Under Bias –55°C to +150°C
V
CC
V
CC
Pin Potential to Ground Pin –0.5V to +7.0V
V
IN
Input Voltage
(1)
–0.5V to +7.0V
I
IN
Input Current
(1)
–30mA to +5.0mA
V
O
Voltage Applied to Any Output
Disabled or Power-Off State
HIGH State
–0.5V to 5.5V
–0.5V to V
CC
Current Applied to Output in LOW State (Max.) twice the rated I
OL
(mA)
DC Latchup Source Current –500mA
Over Voltage Latchup (I/O) 10V
Symbol Parameter Rating
T
A
Free Air Ambient Temperature –40°C to +85°C
V
CC
Supply Voltage +4.5V to +5.5V
∆
V
/
∆
t Minimum Input Edge Rate
Data Input
Enable Input
50mV/ns
20mV/ns
P1-P3P4-P6P7-P9P10-P12P13-P13

74ABT573CSJX

Mfr. #:
Buy 74ABT573CSJX
Manufacturer:
ON Semiconductor
Description:
IC LATCH OCT D-TYPE 3ST 20SOP
Lifecycle:
New from this manufacturer.
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