74ABT16240ADL,118

74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 6 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V. For test circuit, see Figure 6.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
t
PLH
LOW to HIGH
propagation delay
nAn to nYn, see Figure 4 1.0 2.0 3.0 1.0 3.7 ns
t
PHL
HIGH to LOW
propagation delay
nAn to nYn, see Figure 4 1.0 1.5 3.0 1.0 3.5 ns
t
PZH
OFF-state to HIGH
propagation delay
nOE to nYn; see Figure 5 1.2 2.4 3.3 1.2 4.2 ns
t
PZL
OFF-state to LOW
propagation delay
nOE to nYn; see Figure 5 1.2 2.3 3.2 1.0 4.2 ns
t
PHZ
HIGH to OFF-state
propagation delay
nOE to nYn; see Figure 5 1.3 2.7 4.1 1.6 4.7 ns
t
PLZ
LOW to OFF-state
propagation delay
nOE to nYn; see Figure 5 1.3 2.5 3.6 1.4 4.1 ns
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 7 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
11. Waveforms
V
M
= 1.5 V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 4. Input (nAn) to output (nYn) propagation delay
V
M
= 1.5 V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. 3-state output enable and disable times
001aaj892
V
I
V
M
V
M
V
OL
+ 0.3 V
V
OH
0.3 V
V
M
t
PZL
t
PZH
t
PLZ
t
PHZ
GND
3.5 V
V
OL
V
OH
0 V
nOE input
nYn output
nYn output
74ABT16240A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 8 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
12. Test information
V
M
=1.5V
a. Input pulse definition
Test data is given in Table 8.
Definitions test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
b. Test circuit for 3-state outputs
Fig 6. Load circuitry for switching times
001aai298
V
M
V
M
t
W
t
W
10 %
90 % 90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 % 10 %
t
f
t
r
t
r
t
f
001aac764
V
CC
V
I
V
O
V
EXT
R
T
R
L
R
L
C
L
PULSE
GENERATOR
DUT
Table 8. Test data
Input Load V
EXT
V
I
f
i
t
W
t
r
, t
f
C
L
R
L
t
PHZ
, t
PZH
t
PLZ
, t
PZL
t
PLH
, t
PHL
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open 7.0 V open

74ABT16240ADL,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers 16-BIT BUF/DRVR 3-S
Lifecycle:
New from this manufacturer.
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