8-Bit Serial-Input DMOS Power Driver
A6B595
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Note that the A package (DIP) and the LW package
(SOIC) are electrically identical and share a common
terminal number assignment.
PIN-OUT DIAGRAM
GROUND
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
SERIAL
DATA OUT
SERIAL
DATA IN
LOGIC
SUPPLY
V
DD
STROBE
GROUND
CLOCKCLK
ST
OUT
7
OUT
6
OUT
5
Dwg. PP-029-12
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
10
11
NO
CONNECTION
NO
CONNECTION
NCNC
OUTPUT
ENABLE
OE
REGISTER
CLEAR
GROUND
CLR
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name Function
1 NC No internal connection.
2 LOGIC SUPPLY (V
DD
) The logic supply voltage (typically 5 V).
3 SERIAL DATA IN Serial-data input to the shift-register.
4-7 OUT
0-3
Current-sinking, open-drain DMOS output terminals.
8 CLEAR When (active) low, the registers are cleared (set low).
9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
10 GROUND Reference terminal for output voltage measurements (OUT
0-3
).
11 GROUND Reference terminal for output voltage measurements (OUT
0-7
).
12 STROBE Data strobe input terminal; shift register data is latched on rising edge.
13 CLOCK Clock input terminal for data shift on rising edge.
14-17 OUT
4-7
Current-sinking, open-drain DMOS output terminals.
18 SERIAL DATA OUT CMOS serial-data output to the following shift register.
19 GROUND Reference terminal for input voltage measurements.
20 NC No internal connection.
NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally.
