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98ULPA877AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P14
10
ICS98ULPA877A
1177F—12/10/09
Figure 7: Half-Period Jitter
Yx, FB_OUTC
Yx, FB_OUTT
t
JIT(HPER_n)
1
fo
tJIT(HPER_n+1)
tJIT(HPER) =tJIT(HPER_n) -
1
2xfo
Clock Inputs
and outputs
20%
80%
tSLR
20%
80%
tSLF
VID VOD
Figure 8: Input and Output Slew Rates
Parameter Measurement Information
11
ICS98ULPA877A
1177F—12/10/09
Figure 9: Dynamic Phase Offset
Figure 10: Time Delay Between OE and Clock Output (Y, Y#)
CLK#
CLK
FBIN#
FBIN
t( )
t( )dyn
SSC OFF
SSC ON
t( )dyn
t( )
t( )dyn
SSC OFF
SSC ON
t( )dyn
OE
50% V
DDQ
tEN
50% VDDQ
Y. Y#
Y#
Y
OE
50% V
DDQ
tDIS
50% VDDQ
Y#
Y
12
ICS98ULPA877A
1177F—12/10/09
VDDQ
GND
VIA
CARD
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
AVDD
AGND
PLL
1
Figure 11. AVDD Filtering
*Place the 2200pF capacitors close to the PLL.
*Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect
trace to one GND via (farthest from PLL).
*Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 DC max., 600 at 100MHz).
P1-P3P4-P6P7-P9P10-P12P13-P14

98ULPA877AKILFT

Mfr. #:
Buy 98ULPA877AKILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Power 1.8V DDR-I I PLL Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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