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98ULPA877AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P14
4
ICS98ULPA877A
1177F—12/10/09
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V
DDQ
+ 0.5V
Ambient Operating Temperature . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Current
(
CLK_INT, CLK_INC
)
I
IH
V
I
= V
DDQ
or GND
±250 µA
Input Low Current (OE,
OS, FB_INT, FB_INC
)
I
IL
V
I
= V
DDQ
or GND
±10 µA
Output Disabled Low
Current
I
ODL
OE = L, V
ODL
= 100mV
100 µA
I
DD1.8
C
L
= 0pf @ 410MHz
300
mA
I
DDLD
C
L
= 0pf
500
µA
Input Clamp Voltage
V
IK
V
DDQ
= 1.7V Iin = -18mA
-1.2
V
I
OH
= -100 µA
V
DDQ
- 0.2
V
I
OH
= -9 mA
1.1 1.45 V
I
OL
=100 µA
0.25 0.10 V
I
OL
=9 mA
0.6 V
In
p
ut Ca
p
acitance
1
C
IN
V
I
= GND or V
DDQ
23pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DDQ
23pF
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Operating Supply
Current
High-level output voltage
V
OH
Low-level output voltage
V
OL
5
ICS98ULPA877A
1177F—12/10/09
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DDQ
and is the
voltage at which the differential signal must be crossing.
Recommended Operatin
g
Condition
see note1
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DDQ
, A
VDD
1.7 1.8 1.9 V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.35 x V
DDQ
V
OE, OS 0.35 x V
DDQ
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.65 x V
DDQ
V
OE, OS 0.65 x V
DDQ
V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DDQ
+ 0.3 V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3 V
DDQ
+ 0.4 V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.6 V
DDQ
+ 0.4 V
Output differential cross-
volta
g
e (note 4)
V
OX
V
DDQ
/2 - 0.10 V
DDQ
/2 + 0.10 V
Input differential cross-
voltage (note 4)
V
IX
V
DDQ
/2 - 0.15 V
DD
/2 V
DDQ
2 + 0.15 V
High level output current I
OH
-9 mA
Low level output current I
OL
9mA
Operating free-air
temperature
T
A
-40 85 °C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage V
IL
High level input voltage V
IH
6
ICS98ULPA877A
1177F—12/10/09
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (
t
∅), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
Timing Requirements
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency freq
op
1.8V+0.1V @ 25°C
95 410 MHz
Application Frequency
Range
freq
App
1.8V+0.1V @ 25°C 160 410 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
P1-P3P4-P6P7-P9P10-P12P13-P14

98ULPA877AKILFT

Mfr. #:
Buy 98ULPA877AKILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Power 1.8V DDR-I I PLL Clock Driver
Lifecycle:
New from this manufacturer.
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