2
ICS98ULPA877A
1177F—12/10/09
Pin Descriptions
lanimreT
emaN
noitpircseD
lacirtcelE
scitsiretcarahC
DNGAdnuorGgolanA dnuorG
VA
DD
rewopgolanA lanimonV8.1
TNI_KLCrotsisernwodllup)mhOK001-K01(ahtiwtupnikcolC tupnilaitnereffiD
CNI_KLC rotsi
sernwodllup)mhOK001-K01(ahtiwtupnikcolcyratnelpmoC tupnilaitnereffiD
TNI_BFtupnikcolckcabdeeF tupnilaitne
reffiD
CNI_BFtupnikcolckcabdeefyratnemelpmoC tupnilaitnereffiD
TTUO_BFtuptuokcolckcabdeeF tuptuolaitnereffi
D
CTUO_BFtuptuokcolckcabdeefyratnemelpmoC tuptuolaitnereffiD
EO)suonorhcnysA(elbanEtuptuO tupniSOMCVL
SOVroDN
Gotdeit(tceleStuptuO
QDD
)tupniSOMCVL
DNGdnuorG dnuorG
V
QDD
rewoptuptuodnacigoL lanimonV8.1
]9:0[TKLCstuptuokcolC stuptuolaitnereffiD
]9:0[CKLCstuptuokcolcyratnemelpmo
C stuptuolaitnereffiD
BNllaboN
The PLL clock buffer, ICS98ULPA877A, is designed for a V
DDQ
of 1.8 V, a AV
DD
of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or V
DDQ
. When OS is high, OE will function as described above. When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
STAB
.
The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
