–2–
REV. A
AD7545–SPECIFICATIONS
V
DD
= +5 V V
DD
= +15 V
Limits Limits
Parameter Version T
A
= + 25ⴗCT
MIN,
T
MAX
1
T
A
= + 25ⴗCT
MIN,
T
MAX
1
Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution All 12 12 12 12 Bits
J, A, S ±2 ±2 ±2 ±2 LSB max
K, B, T ±1 ±1 ±1 ±1 LSB max
L, C, U ±1/2 ±1/2 ±1/2 ±1/2 LSB max
GL, GC, GU ±1/2 ±1/2 ±1/2 ±1/2 LSB max
Differential Nonlinearity J, A, S ±4 ±4 ±4 ±4 LSB max 10-Bit Monotonic T
MIN
to T
MAX
K, B, T ±1 ±1 ±1 ±1 LSB max 12-Bit Monotonic T
MIN
to T
MAX
L, C, U ±1 ±1 ±1 ±1 LSB max 12-Bit Monotonic T
MIN
to T
MAX
GL, GC, GU ±1 ±1 ±1 ±1 LSB max 12-Bit Monotonic T
MIN
to T
MAX
Gain Error (Using Internal RFB)
2
J, A, S ±20 ±20 ±25 ±25 LSB max DAC Register Loaded with
K, B, T ±10 ±10 ±15 ±15 LSB max 1111 1111 1111
L, C, U ±5 ±6 ±10 ± 10 LSB max Gain Error Is Adjustable Using
GL, GC, GU ±1 ±2 ±6 ±7 LSB max the Circuits of Figures 4, 5, and 6
Gain Temperature Coefficient
3
∆Gain/∆Temperature All ±5 ±5 ±10 ± 10 ppm/°C max Typical Value is 2 ppm/°C for V
DD
= +5 V
DC Supply Rejection
3
∆Gain/∆V
DD
All 0.015 0.03 0.01 0.02 % per % max ∆V
DD
= ±5%
Output Leakage Current at OUT1 J, K, L, GL 10 50 10 50 nA max DB0–DB11 = 0 V; WR, CS = 0 V
A, B, C, GC 10 50 10 50 nA max
S, T, U, GU 10 200 10 200 nA max
DYNAMIC PERFORMANCE
Current Settling Time
3
All 2 2 2 2 µs max To 1/2 LSB. OUT1 Load = 100 Ω. DAC
Output Measured from Falling Edge of
WR, CS = 0.
Propagation Delay
3
(from Digital
Input Change to 90%
of Final Analog Output) All 300 – 250 – ns max OUT1 Load = 100 Ω, C
EXT
= 13 pF
4
Digital-to-Analog Glitch Inpulse All 400 – 250 – nV sec typ V
REF
= AGND
AC Feedthrough
5
At OUT1 All 5 5 5 5 mV p-p typ V
REF
= ±10 V, 10 kHz Sinewave
REFERENCE INPUT
Input Resistance All 7 7 7 7 kΩ min Input Resistance TC = –300 ppm/°C typ
(Pin 19 to GND) 25 25 25 25 kΩ max Typical Input Resistance = 11 kΩ
ANALOG OUTPUT
Output Capacitance
3
C
OUT1
All 70 70 70 70 pF max DB0–DB11 = 0 V, WR, CS = 0 V
C
OUT1
200 200 200 200 pF max DB0–DB11 = V
DD
, WR, CS = 0 V
DIGITAL INPUTS
Input High Voltage
V
IH
All 2.4 2.4 13.5 13.5 V min
Input Low Voltage
V
IL
All 0.8 0.8 1.5 1.5 V max
Input Current
6
I
IN
All ±1 ±10 ±1 ±10 µA max V
IN
= 0 or V
DD
Input Capacitance
3
DB0–DB11 All 5 5 5 5 pF max V
IN
= 0
WR, CS All 20 20 20 20 pF max V
IN
= 0
SWITCHING CHARACTERISTICS
7
Chip Select to Write Setup Time All 280 380 180 200 ns min See Timing Diagram
t
CS
200 270 120 150 ns typ
Chip Select to Write Hold Time
t
CH
All 0 0 0 0 ns min
Write Pulse Width
t
WR
All 250 400 160 240 ns min t
CS
≥ t
WR
, t
CH
≥ 0
175 280 100 170 ns typ
Data Setup Time All 140 210 90 120 ns min
t
DS
100 150 60 80 ns typ
Data Hold Time
t
DH
All 10 10 10 10 ns min
POWER SUPPLY
I
DD
All 2 2 2 2 mA max All Digital Inputs V
IL
or V
IH
100 500 100 500 µA max All Digital Inputs 0 V to V
DD
10 10 10 10 µA typ All Digital Inputs 0 V to V
DD
NOTES
1
Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.
2
This includes the effect of 5 ppm max gain TC.
3
Guaranteed but not tested.
4
DB0–DB11 = 0 V to V
DD
or V
DD
to 0 V.
5
Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.
6
Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.
7
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
(V
REF
= +10 V, V
OUT1
= O V, AGND = DGND unless otherwise noted)
