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AD7545ALNZ

P1-P3P4-P6P7-P9
AD7545
–3–REV. A
ABSOLUTE MAXIMUM RATINGS*
(T
A
= + 25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
V
PIN1
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
TERMINOLOGY
RELATIVE ACCURACY
The amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
measurement.
DIFFERENTIAL NONLINEARITY
The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V
REF
= AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
1
Maximum
Gain Error
Temperature Relative T
A
= +25ⴗC Package
Model
2
Range Accuracy V
DD
= +5 V Options
3
AD7545JN 0°C to +70°C ±2 LSB ±20 LSB N-20
AD7545AQ –25°C to +85°C ±2 LSB ±20 LSB Q-20
AD7545SQ –55°C to +125°C ±2 LSB ±20 LSB Q-20
AD7545KN 0°C to +70°C ± 1 LSB ±10 LSB N-20
AD7545BQ –25°C to +85°C ±1 LSB ±10 LSB Q-20
AD7545TQ –55°C to +125°C ±1 LSB ±10 LSB Q-20
AD7545LN 0°C to +70°C ±1/2 LSB ±5 LSB N-20
AD7545CQ –25°C to +85°C ±1/2 LSB ±5 LSB Q-20
AD7545UQ –55°C to +125°C ± 1/2 LSB ±5 LSB Q-20
AD7545GLN 0°C to +70°C ±1/2 LSB ±1 LSB N-20
AD7545GCQ –25°C to +85°C ±1/2 LSB ±1 LSB Q-20
AD7545GUQ –55°C to +125°C ±1/2 LSB ±1 LSB Q-20
AD7545JP 0°C to +70°C ±2 LSB ±20 LSB P-20A
AD7545SE –55°C to +125°C ±2 LSB ±20 LSB E-20A
AD7545KP 0°C to +70°C ±1 LSB ±10 LSB P-20A
AD7545TE –55°C to +125°C ±1 LSB ±10 LSB E-20A
AD7545LP 0°C to +70°C ±1/2 LSB ±5 LSB P-20A
AD7545UE –55°C to +125°C ±1/2 LSB ±5 LSB E-20A
AD7545GLP 0°C to +70°C ±1/2 LSB ±1 LSB P-20A
AD7545GUE –55°C to +125°C ± 1/2 LSB ±1 LSB E-20A
NOTES
1
Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).
2
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
Write Cycle Timing Diagram
CHIP
SELECT
WRITE
DATA IN
(DB0–DB11)
V
DD
0
V
DD
0
V
DD
0
DATA VALID
V
IH
V
IL
t
DS
t
DH
t
WR
t
CS
t
CH
MODE SELECTION
CS AND WR LOW, DAC RESPONDS
TO DATA BUS (DB0–DB11) INPUTS.
WRITE MODE:
HOLD MODE:
EITHER CS OR WR HIGH, DATA BUS
(DB0–DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
WR OR CS ASSUMED HIGH STATE.
NOTES:
V
DD
= +5V; t
r
= t
f
= 20ns
V
DD
= +15V; t
r
= t
f
= 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF V
DD
.
TIMING MEASUREMENT REFERENCE LEVEL IS V
IH
+ V
IL
/2.
AD7545
–4–
REV. A
CIRCUIT INFORMATION—D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 kΩ.
2R 2R 2R 2R 2R 2R
RRR R
V
REF
R
FB
OUT 1
AGND
DB11
(MSB)
DB0
(LSB)
DB10 DB9 DB1
Figure 1. Simplified D/A Circuit of AD7545
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
The capacitance at the OUT1 bus line, C
OUT1
, is code depen-
dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at V
REF
(Figure 1) is always equal to R
LDR
(R
LDR
is
the R/2R ladder characteristic resistance and is equal to value
“R”). Since R
IN
at the V
REF
pin is constant, the reference termi-
nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external R
FB
is recommended
to define scale factor.)
TO LADDER
AGND OUT 1
FROM
INTERFACE
LOGIC
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTION
Figure 3 shows the digital structure for one bit.
The digital signals CONTROL and CONTROL are generated
from CS and WR.
V
IN
INPUT BUFFERS
CONTROL
CONTROL
TO AGND SWITCH
TO OUT1 SWITCH
Figure 3. Digital Input Structure
The input buffers are simple CMOS inverters designed so that
when the AD7545 is operated with V
DD
= 5 V, the buffers con-
vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.
When V
IN
is in the region of 2.0 volts to 3.5 volts, the input
buffers operate in their linear region and draw current from the
power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (V
DD
and DGND).
The AD7545 may be operated with any supply voltage in the
range 5 ≤ V
DD
≤ 15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of ±1 LSB at +25°C
(V
DD
= +5 V), and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the V
REF
terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –V
IN
(note the inversion introduced by the op amp),
or V
IN
can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). V
IN
can be any voltage
in the range –20 ≤ V
IN
+ 20 volts (provided the op amp can
handle such voltages) since V
REF
is permitted to exceed V
DD
.
Table II shows the code relationship for the circuit of Figure 4.
V
DD
R1
*
V
IN
DB11–DB0
ANALOG
COMMON
R2
*
C1
33pF
AD544L
(SEE TEXT)
V
OUT
*
REFER TO TABLE I
2018
1
2
3
19
AD7545
V
DD
R
FB
V
REF
DGND
OUT1
AGND
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades for
V
DD
= +5 V
Trim
Resistor J/A/S K/B/T L/C/U GL/GC/GU
R1 500 Ω 200 Ω 100 Ω 20 Ω
R2 150 Ω 68 Ω 33 Ω 6.8 Ω
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC Register Analog Output
1 1 1 1 1 1 1 1 1 1 1 1 –V
IN
4095
4096
1 0 0 0 0 0 0 0 0 0 0 0 –V
IN
2048
4096
= –1/2 V
IN
0 0 0 0 0 0 0 0 0 0 0 1 –V
IN
1
4096
0 0 0 0 0 0 0 0 0 0 0 0 0 Volts
AD7545
–5–REV. A
Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U
1
on the MSB line con-
verts twos complement input code to offset binary code. If ap-
propriate; inversion of the MSB may be done in software using
an exclusive –OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01% and they should
be the same type of resistor (preferably wire-wound or metal
foil), so their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full-scale error. Mismatch of
R5 and R4 and R3 causes full-scale error.
A1
R2
*
V
DD
R1
*
V
IN
DATA INPUT
ANALOG
COMMON
C1
33pF
AD544L
V
OUT
AD544J
A2
R4
20kΩ
R5
20kΩ
R3
10kΩ
R6
5kΩ
10%
*
FOR VALUES OF R1 AND R2
SEE TABLE I.
11
12
AD7545
18
19
20
1
2
V
DD
R
FB
V
REF
DB10–DB0
OUT1
AGND
4
DB11
U
1
(SEE TEXT)
Figure 5. Bipolar Operation (Twos Complement Code)
Table III. Twos Complement Code Table for Circuit of
Figure 5
Data Input Analog Output
0 1 1 1 1 1 1 1 1 1 1 1 +V
IN
×
2047
2048
0 0 0 0 0 0 0 0 0 0 0 1 +V
IN
×
1
2048
0 0 0 0 0 0 0 0 0 0 0 0 0 Volts
1 1 1 1 1 1 1 1 1 1 1 1 –V
IN
×
1
2048
1 0 0 0 0 0 0 0 0 0 0 0 –V
IN
×
2048
2048
Figure 6 shows an alternative method of achieving bipolar out-
put. The circuit operates with sign plus magnitude code and has
the advantage of giving 12-bit resolution in each quadrant, com-
pared with 11-bit resolution per quadrant for the circuit of Fig-
ure 5. The AD7592 is a fully protected CMOS change-over
switch with data latches. R4 and R5 should match each other to
0.01% to maintain the accuracy of the D/A converter. Mismatch
between R4 and R5 introduces a gain error.
A2
A1
R2
*
V
DD
R1
*
V
IN
ANALOG
COMMON
C1
33pF
AD544L
V
OUT
AD544J
R5
20kΩ
*
FOR VALUES OF R1 AND R2
SEE TABLE I.
R4
20kΩ
R3
10kΩ
10%
1/2 AD7592JN
SIGN BIT
12
AD7545
3
18
19
20
1
2
V
DD
R
FB
V
REF
DB11–DB0
OUT1
AGND
Figure 6. 12-Bit Plus Sign Magnitude D/A Converter
Table IV. 12-Plus Sign Magnitude Code Table for Circuit of
Figure 6
Sign Binary Number in DAC
Bit MSB LSB Analog Output, V
OUT
0 1 1 1 1 1 1 1 1 1 1 1 1 + V
IN
×
4095
4096
0 0 0 0 0 0 0 0 0 0 0 0 0 0 Volts
1 0 0 0 0 0 0 0 0 0 0 0 0 0 Volts
1 1 1 1 1 1 1 1 1 1 1 1 1 – V
IN
×
4095
4096
Note: Sign bit of “0” connects R3 to GND.
APPLICATIONS HINTS
Output Offset: (CMOS D/A converters exhibit a code depen-
dent output resistance which, in turn, causes a code dependent
amplifier noise gain. The effect is a code dependent differential
nonlinearity term at the amplifier output that depends on V
OS
where V
OS
is the amplifier input offset voltage. To maintain
monotonic operation it is recommended that V
OS
be no greater
than 25 × 10
–6
) (V
REF
) over the temperature range of operation.
Suitable op amps are AD517L and AD544L. The AD517L is
best suited for fixed reference applications with low bandwidth
requirements: it has extremely low offset (50 µV) and in most
applications will not require an offset trim. The AD544L has a
much wider bandwidth and higher slew rate and is recommended
for multiplying and other applications requiring fast settling. An
offset trim on the AD544L may be necessary in some circuits.
General Ground Management: AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel
between the AD7545 AGND and DGND pins (IN914 or
equivalent).
Digital Glitches: When WR and CS are both low the latches
are transparent and the D/A converter inputs follow the data
inputs. In some bus systems, data on the data bus is not always
valid for the whole period during which WR is low and as a
result invalid data can briefly occur at the D/A converter inputs
during a write cycle. Such invalid data can cause unwanted
glitches at the output of the D/A converter. The solution to this
problem, if it occurs, is to retime the write pulse WR so that it
only occurs when data is valid.
Another cause of digital glitches is capacitive coupling from the
digital lines to the OUT1 and AGND terminals. This should be
minimized by screening the analog pins of the AD7545 (Pins 1,
2, 19, 20) from the digital pins by a ground track run between
Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note
how the analog pins are at one end of the package and separated
from the digital pins by V
DD
and DGND to aid screening at
the board level. On-chip capacitive coupling can also give rise
to crosstalk from the digital-to-analog sections of the AD7545,
particularly in circuits with high currents and fast rise and
fall times. This type of crosstalk is minimized by using
P1-P3P4-P6P7-P9

AD7545ALNZ

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Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12B CMOS IC Buffered Multiplying
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