AD7880
REV. 0
–3–
TIMING CHARACTERISTICS
1
Limit at +258C Limit at T
MIN
, T
MAX
Parameter (All Versions) (All Versions) Units Conditions/Comments
t
1
50 50 ns min CONVST Pulse Width
t
2
130 130 ns min CONVST to BUSY Falling Edge
t
3
0 0 ns min BUSY to CS Setup Time
t
4
0 0 ns min CS to RD Setup Time
t
5
0 0 ns min CS to RD Hold Time
t
6
60 75 ns min RD Pulse Width
t
7
2
57 70 ns max Data Access Time after RD
t
8
3
55 ns min Bus Relinquish Time after RD
50 50 ns max
NOTES
1
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
7
is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
8
is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
(V
DD
= +5 V 6 5%, V
REF
= V
DD
, AGND = DGND = 0 V)
Table I. Truth Table
CS CONVST RD Function
1 1 X Not Selected
1 j 1 Start Conversion g
0 1 0 Enable ADC Data
0 1 1 Data Bus Three Stated
ABSOLUTE MAXIMUM RATINGS*
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
INA
, V
INB
to AGND (Figure 5) . . . . . . –0.3 V to V
DD
+ 0.3 V
V
INA
to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 V
DD
+ 0.6 V
V
INA
to AGND (Figure 7) . . . . . –V
DD
– 0.3 V to V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7880 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DB0 – DB11
DATA
VALID
t
1
t
CONVERT
t
2
t
3
t
4
t
5
t
6
t
7
t
8
CONVST
BUSY
CS
RD
THREE-STATE
TRACK/HOLD
GOES INTO HOLD
Figure 1. Timing Diagram
TO OUTPUT
PIN
1.6mA
2.1V+
200µA
50pF
Figure 2. Load Circuit for Access and Relinquish Time
AD7880
–4–
REV. 0
PIN FUNCTION DESCRIPTION
Pin Pin
No. Mnemonic Function
1V
INA
Analog Input.
2V
INB
Analog Input.
3 AGND Analog Ground.
4V
REF
Voltage Reference Input. This is normally tied to V
DD
.
5
CS Chip Select. Active Low Logic input. The device is selected when this input is active.
6
CONVST Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con-
version. This input is asynchronous to the CLKIN and is independent of
CS and RD.
7
RD Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs.
8
BUSY Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion.
9 CLKIN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/
space ratio of the clock can vary from 40/60 to 60/40.
10 DGND Digital Ground.
11 . . . 22 DB0–DB11 Three-State Data Outputs. These become active when
CS and RD are brought low.
23 MODE MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During
normal operation, the MODE input will be a logic high (MODE = V
DD
).
24 V
DD
Power Supply. This is nominally +5 V.
ORDERING GUIDE
Bipolar
Full-Scale Zero
Temperature Error Error Package
Model Range (LSBs) (LSBs) Option*
AD7880BN –40°C to +85°C ±15 ±10 N-24
AD7880BQ –40°C to +85°C ±15 ±10 Q-24
AD7880CN –40°C to +85°C ±5 ±5 N-24
AD7880CQ –40°C to +85°C ±5 ±5 Q-24
AD7880BR –40°C to +85°C ±15 ±10 R-24
AD7880CR –40°C to +85°C ±5 ±5 R-24
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
AD7880
AGND
CLKIN
DGND
DB0
DB1 DB2
DB3
DB4
DB5
DB6
V
DD
DB8
V
INA
V
INB
DB7
DB9
DB10
DB11
MODE
CS
CONVST
RD
BUSY
V
REF
AD7880
REV. 0
–5–
+
R
V
INA
V
INB
R
V
DAC
Figure 4. AD7880 Input Circuit
The AD7880 accommodates three separate input ranges, 0 to
V
REF
, 0 to 2 V
REF
and ±V
REF
. The input configurations corre-
sponding to these ranges are shown in Figures 5, 6 and 7.
With V
REF
= V
DD
and using a nominal V
DD
of +5 V, the input
ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in
Table II.
Table II. Analog Input Ranges
Analog Input
Input Connections
Connection
Range V
REF
V
INA
V
INB
Diagram
0 V to +5 V V
DD
V
IN
V
IN
Figure 5
0 V to +10 V V
DD
V
IN
AGND Figure 6
±5 V V
DD
V
IN
V
REF
Figure 7
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO V
REF
V
IN
Figure 5. 0 to V
REF
Unipolar Input Configuration
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO 2V
REF
V
IN
Figure 6. 0 to 2 V
REF
Unipolar Input Configuration
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= V
REF
V
IN
±
Figure 7.
±
V
REF
Bipolar Input Configuration
CIRCUIT INFORMATION
The AD7880 is a +5 V single supply 12-bit A/D converter. The
part requires no external components apart from a 2.5 MHz ex-
ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7880 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 66 kHz.
CONVERTER DETAILS
The AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the
CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 12 µs. This corresponds to a conversion cycle
time of 28 clock periods with a CLKIN frequency of 2.5 MHz
and also includes internal propagation delays. During conver-
sion the
BUSY output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the
BUSY output will go to a high level, and the result of the
conversion can be read by bringing
CS and RD low.
The track/hold amplifier acquires a 12-bit input signal in 3 µs.
The overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a
2.5 MHz input clock the throughput time is 15 µs.
REFERENCE INPUT
For specified performance, it is recommended that the reference
input be tied to V
DD
. The part, however, will operate with a ref-
erence down to 2.5 V though with reduced performance specifi-
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
versus V
REF
.
V
REF
must not be allowed to go above V
DD
by more than
100 mV.
74
72
70
68
66
64
62
60
2345
V
REF
– Volts
SNR
– dBs
F = 51.2kHz
S
F = 2.525kHz
IN
T = 25 C
A
Figure 3. SNR vs. V
REF
ANALOG INPUT
The AD7880 has two analog input pins, V
INA
and V
INB
. Figure
4 shows the input circuitry to the ADC sampling comparator.
The on-board attenuator network, made up of equal resistors,
allows for various input ranges.

AD7880BN

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS SGL +5V Supply Lo Pwr 12B Sampling
Lifecycle:
New from this manufacturer.
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