AD7880BN Datasheet AD7880CRZ, AD7880BNZ, AD7880CNZ | P7-P9

AD7880

–6–

REV. 0

The AD7880 has two unipolar input ranges, 0 V to 5 V and 0 V

to 10 V. Figure 5 shows the analog input for the 0 V to 5 V

range. The designed code transitions occur midway between

successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,

5/2 LSBs . . . FS –3/2 LSBs). The output code is straight binary

with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The same applies

for the 0 V to 10 V range, as shown in Figure 6, except that the

LSB size is bigger. In this case 1 LSB = FS/4096 = 10 V/4096 =

2.44 mV. The ideal input/output transfer characteristic for both

these unipolar ranges is shown in Figure 8.

1LSB =

4096

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...001

000...000

000...010

V INPUT VOLTAGE

1LSB

FS – 1LSB

Figure 8. AD7880 Unipolar Transfer Characteristic

Figure 7 shows the AD7880’s ±5 V bipolar analog input con-

figuration. Once again the designed code transitions occur mid-

way between successive integer LSB values. The output code is

straight binary with 1 LSB = FS/4096 = 10 V/4096 = 2.44 mV.

The ideal bipolar input/output transfer characteristic is shown in

Figure 9.

–

FS = 10V

1LSB =

4096

OUTPUT

CODE

111...111

111...110

100...101

100...000

011...111

011...110

000...001

000...000

1LSB–

V INPUT VOLTAGE

1LSB

–

1LSB+

Figure 9. AD7880 Bipolar Transfer Characteristic

CLOCK INPUT

The AD7880 is specified to operate with a 2.5 MHz clock con-

nected to the CLKIN input pin. This pin may be driven directly

by CMOS or TTL buffers. The mark/space ratio on the clock

can vary from 40/60 to 60/40. As the clock frequency is slowed

down, it can result in slightly degraded accuracy performance.

This is due to leakage effects on the hold capacitor in the inter-

nal track-and-hold amplifier. Figure 10 is a typical plot of accu-

racy versus clock frequency for the ADC.

2.5

2.0

1.5

1.0

0.5

0.0

0.5

1.5 2.5 3.5

CLOCK FREQUENCY – MHz

NORMALIZED LINEARITY ERROR

Figure 10. Normalized Linearity Error vs. Clock Frequency

TRACK/HOLD AMPLIFIER

The charge balanced comparator used in the AD7880 for the

A/D conversion provides the user with an inherent track/hold

function. The track/hold amplifier acquires an input signal to

12-bit accuracy in less than 3 µs. The overall throughput time is

equal to the conversion time plus the track/hold amplifier acqui-

sition time. For a 2.5 MHz input clock, the throughput time is

15 µs.

The operation of the track/hold amplifier is essentially transpar-

ent to the user. The track/hold amplifier goes from its tracking

mode to its hold mode at the start of conversion, i.e., on the ris-

ing edge of

CONVST as shown in Figure 1.

OFFSET AND FULL-SCALE ADJUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Some applications will require that the input

signal range match the maximum possible dynamic range of the

ADC. In such applications, offset and full-scale error will have

to be adjusted to zero.

The following sections describe suggested offset and full-scale

adjustment techniques which rely on adjusting the inherent off-

set of the op amp driving the input to the ADC as well as tweak-

ing an additional external potentiometer as shown in Figure 11.

AD7880

REV. 0

–7–

–

10 kΩ

INA

AGND

AD7880*

500 Ω

10 kΩ

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 11. Offset and Full-Scale Adjust Circuit

Unipolar Adjustments

In the case of the 0 V to 5 V unipolar input configuration, unipolar

offset error must be adjusted before full-scale error. Adjustment is

achieved by trimming the offset of the op amp driving the ana-

log input of the AD7880. This is done by applying an input

voltage of 0.61 mV (1/2 LSB) to V

in Figure 11 and adjusting

the op amp offset voltage until the ADC output code flickers

between 0000 0000 0000 and 0000 0000 0001. For full-scale

adjustment, an input voltage of 4.9982 V (FS–3/2 LSBs) is

applied to V

and R2 is adjusted until the output code flickers

between 1111 1111 1110 and 1111 1111 1111.

The same procedure is required for the 0 V to 10 V input con-

figuration of Figure 6. An input voltage of 1.22 mV (1/2 LSB) is

applied to V

in Figure 11 and the op amp’s offset voltage is

adjusted until the ADC output code flickers between 0000 0000

0000 and 0000 0000 0001. For full-scale adjustment, an input

voltage of 9.9963 V (FS–3/2 LSBs) is applied to V

and R2 is

adjusted until the output code flickers between 1111 1111 1110

and 1111 1111 1111.

Bipolar Adjustments

Bipolar zero and full-scale errors for the bipolar input configura-

tion of Figure 7 are adjusted in a similar fashion to the unipolar

case. Again, bipolar zero error must be adjusted before full-scale

error. Bipolar zero error adjustment is achieved by trimming the

offset of the op amp driving the analog input of the AD7880

while the input voltage is 1/2 LSB below ground. This is done

by applying an input voltage of –1.22 mV (1/2 LSB) to V

Figure 11 and adjusting the op amp offset voltage until the

ADC output code flickers between 0111 1111 1111 and 1000

0000 0000. For full-scale adjustment, an input voltage of

4.9982 V (FS/2–3/2 LSBs) is applied to V

and R2 is adjusted

until the output code flickers between 1111 1111 1110 and

1111 1111 1111.

DYNAMIC SPECIFICATIONS

The AD7880 is specified and tested for dynamic performance

specifications as well as traditional dc specifications such as

integral and differential nonlinearity. The ac specifications are

required for signal processing applications such as speech recog-

nition, spectrum analysis and high speed modems. These appli-

cations require information on the ADC’s effect on the spectral

content of the input signal. Hence, the parameters for which the

AD7880 is specified include SNR, harmonic distortion, inter-

modulation distortion and peak harmonics. These terms are dis-

cussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

ADC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (FS/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal to noise ratio for a sine wave input

is given by:

SNR = (6.02 N + 1.76) dB (1)

where N is the number of bits.

Thus for an ideal 12-bit converter, SNR = 74 dB.

The output spectrum from the ADC is evaluated by applying a

sine wave signal of very low distortion to the V

input which is

sampled at a 66 kHz sampling rate. A Fast Fourier Transform

(FFT) plot is generated from which the SNR data can be ob-

tained. Figure 12 shows a typical 2048 point FFT plot of the

AD7880 with an input signal of 2.5 kHz and a sampling fre-

quency of 61 kHz. The SNR obtained from this graph is 73dB.

It should be noted that the harmonics are taken into account

when calculating the SNR.

Figure 12. FFT Plot

Effective Number of Bits

The formula given in Equation 1 relates the SNR to the number

of bits. Rewriting the formula, as in Equation 2, it is possible to

get a measure of performance expressed in effective number of

bits (N).

N =

SNR −1. 76

6.02

(2)

The effective number of bits for a device can be calculated

directly from its measured SNR.

Figure 13 shows a plot of effective number of bits versus input

frequency for an AD7880 with a sampling frequency of 61 kHz.

The effective number of bits typically remains better than 11.5

for frequencies up to 12 kHz.

AD7880

–8–

REV. 0

11.5

10.5

INPUT FREQUENCY – kHz

SAMPLE FREQUENCY = 61kHz

T = 25 C

15 30.5

EFFECTIVE NUMBER OF BITS

Figure 13. Effective Number of Bits vs. Frequency

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the rms value

of the fundamental. For the AD7880, THD is defined as:

THD = 20log

(3)

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonic. The THD is also derived from the FFT plot of

the ADC output spectrum.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which

neither m nor n are equal to zero. For example, the second or-

der terms include (fa + fb) and (fa – fb), while the third order

terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Using the CCIF standard where two input frequencies near the

top end of the input bandwidth are used, the second and third

order terms are of different significance. The second order terms

are usually distanced in frequency from the original sine waves,

while the third order terms are usually at a frequency close to

the input frequencies. As a result, the second and third order

terms are specified separately. The calculation of the inter-

modulation distortion is as per the THD specification where it is

the ratio of the rms sum of the individual distortion products to

the rms amplitude of the fundamental expressed in dBs. In this

case, the input consists of two, equal amplitude, low distortion,

sine waves. Figure 14 shows a typical IMD plot for the

AD7880.

Figure 14. IMD Plot

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to FS/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification will be

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor the peak

will be a noise peak.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7880BN

Mfr. #:

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Description:

Analog to Digital Converters - ADC CMOS SGL +5V Supply Lo Pwr 12B Sampling

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AD7880BN

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