PCA9508_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 April 2008 11 of 21
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
10. Dynamic characteristics
[1] Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on the B side, and 167 Ω pull-up resistance
and 57 pF load capacitance on the A side. Different load resistance and capacitance will alter the RC time constant, thereby changing
the propagation delay and transition times.
[2] Pull-up voltages are V
CC(A)
on the A side and V
CC(B)
on the B side.
[3] Typical values were measured with V
CC(A)
= 3.3 V at T
amb
=25°C, unless otherwise noted.
[4] The t
PLH
delay data from B side to A side is measured at 0.5 V on the B side to 0.5V
CC(A)
on the A side when V
CC(A)
is less than 2 V, and
1.5 V on the A side if V
CC(A)
is greater than 2 V.
[5] Typical value measured with V
CC(A)
= 2.7 V at T
amb
=25°C.
[6] The proportional delay data from A side to B side is measured at 0.3V
CC(A)
on the A side to 1.5 V on the B side.
[7] Defined as the time required to connect from B side to A side, after B side switches from active to idle, when A side is idle.
[8] Defined as the time required to connect from B side to A side, when B side and A side are idle.
[9] Defined as the time required to connect A side to B side, when B side is idle and A side is going active from idle, by a STOP condition.
[10] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
Table 6. Dynamic characteristics
V
CC
=2.7V to 5.5V; GND=0V; T
amb
=
−
40
°
Cto+85
°
C; unless otherwise specified.
[1][2]
Symbol Parameter Conditions Min Typ
[3]
Max Unit
t
PLH
LOW-to-HIGH propagation delay B side to A side; Figure 11
[4]
100 170 250 ns
t
PHL
HIGH-to-LOW propagation delay B side to A side; Figure 9
V
CC(A)
< 3.0 V
[5]
20 98 118 ns
V
CC(A)
> 3.0 V 20 76 164 ns
t
TLH
LOW to HIGH output transition time A side; Figure 10 10 20 30 ns
t
THL
HIGH to LOW output transition time A side; Figure 10
V
CC(A)
< 2.7 V
[5]
1 7283ns
V
CC(A)
> 3.0 V 8 68 137 ns
t
PLH
LOW-to-HIGH propagation delay A side to B side; Figure 10
[6]
25 53 110 ns
t
PHL
HIGH-to-LOW propagation delay A side to B side; Figure 10
[6]
60 79 230 ns
t
TLH
LOW to HIGH output transition time B side; Figure 9 120 140 170 ns
t
THL
HIGH to LOW output transition time B side; Figure 9 30 48 90 ns
t
connect
connect time
[7]
B side to A side; Figure 12 - 0.5 - µs
t
idle(connect)
connect idle time
[8]
B side to A side; Figure 13 50 105 200 µs
t
stop(connect)
connect stop time
[9]
A side to B side; Figure 14 - 0.5 - µs
t
su
set-up time EN HIGH before START condition
[10]
100 - - ns
t
h
hold time EN HIGH after STOP condition
[10]
100 - - ns
