RMLV0808BGSB - 4S2
R10DS0232EJ0200 Rev.2.00 Page 11 of
11
2015.06.26
Low V
CC
Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*28
V
CC
for data retention V
DR
1.5 ─ 3.6 V
Vin ≥ 0V,
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ V
CC
-0.2V, CS2 ≥ V
CC
-0.2V
Data retention current I
CCDR
─ 0.45
*26
2 A ~+25°C
V
CC
= 3.0V, Vin ≥ 0V,
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ V
CC
-0.2V,
CS2 ≥ V
CC
-0.2V
─ 0.6
*27
4 A ~+40°C
─ ─ 7 A ~+70°C
─ ─ 10 A ~+85°C
Chip deselect time to data retention t
CDR
0 ─ ─ ns
See retention waveform.
Operation recovery time t
R
5 ─ ─ ms
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
28. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and DQ buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1#
controls data retention mode, CS2 must be CS2 ≥ V
CC
-0.2V or CS2 ≤ 0.2V. The other inputs levels (address,
WE#, OE#, DQ) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS1# controlled)
Low Vcc Data Retention Timing Waveforms (CS2 controlled)
CS1#
V
CC
CS1# Controlled
t
CDR
t
R
2.4V 2.4V
2.0V 2.0V
DR
CS1# ≥
-0.2V
CS2
V
CC
CS2 Controlled
t
CDR
t
R
2.4V 2.4V
0.4V 0.4V
DR
CS2 ≤ 0.2V
